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Proceedings of the 30th European Solid-State Circuits Conference最新文献

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A 2.4GHz-bandwidth OEIC with voltage-up-converter [optical receiver] 带电压上转换器的2.4 ghz带宽OEIC[光接收机]
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356658
R. Swoboda, J. Knorr, H. Zimmermann
{"title":"A 2.4GHz-bandwidth OEIC with voltage-up-converter [optical receiver]","authors":"R. Swoboda, J. Knorr, H. Zimmermann","doi":"10.1109/ESSCIR.2004.1356658","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356658","url":null,"abstract":"This work describes a realisation of an optoelectronic integrated circuit (OEIC) with an integrated voltage-up-converter (VUC) to enhance the frequency response of an integrated pin photodiode. The VUC produces a voltage of 11 V and improves the bandwidth of the OEIC from 1.5 GHz to 2.4 GHz for a single 5 V supply without any additional external components. For a maximum measured data rate of 3 Gbps and a bit error rate of 10/sup -9/ a sensitivity of -24.3 dBm at a wavelength of 660 nm is obtained. The OEIC is implemented in a modified 0.6 /spl mu/m silicon BiCMOS technology with f/sub T/=25 GHz.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-power clock generator for system-on-a-chip (SoC) processors 用于片上系统(SoC)处理器的低功耗时钟发生器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356701
Amir M. Fahim
{"title":"A low-power clock generator for system-on-a-chip (SoC) processors","authors":"Amir M. Fahim","doi":"10.1109/ESSCIR.2004.1356701","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356701","url":null,"abstract":"This paper describes a low-power, low-jitter clock generator for system-on-a-chip (SoC) processors. Low-jitter is achieved by using a ROM-less direct digital synthesizer with analog phase interpolation. Low-power is achieved by using differential and feedback replica bias circuit topologies. A 6-bit resolution prototype is implemented in 0.25 /spl mu/m CMOS technology. Results demonstrate that the clock generator's area is 0.12 mm/sup 2/ and consumes only 1.5 mA of current consumption at 2.5 V. In comparison with other similar state-of-the-art implementations, this represents savings of 37.5/spl times/ and 5.87/spl times/ in area and power consumption, respectively.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 100 MHz timing generator for impulse radio applications 用于脉冲无线电应用的100mhz定时发生器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356712
Chun-Pang Wu, H. Tsao
{"title":"A 100 MHz timing generator for impulse radio applications","authors":"Chun-Pang Wu, H. Tsao","doi":"10.1109/ESSCIR.2004.1356712","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356712","url":null,"abstract":"The timing generator is used to generate a 100 MHz timing signal for impulse radio system with timing resolution of 19.5 ps controlled by 9-bit digital input. A fine phase interpolator is used to generate one of the 32 interpolated phases by using common gate buffered switch techniques. The timing generator achieves /spl plusmn/0.3LSB differential nonlinearity and /spl plusmn/2LSB integral nonlinearity. The chip is fabricated in a standard 0.35 /spl mu/m CMOS process and consumes 55 mW power from a 3 V supply. The chip area including pads occupies 1.5/spl times/1.5 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128698345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A multi-mode continuously-tunable lowpass filter for zero-IF mobile applications 零中频移动应用的多模连续可调低通滤波器
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356626
D. Chamla, A. Kaiser, A. Cathelin, D. Belot
{"title":"A multi-mode continuously-tunable lowpass filter for zero-IF mobile applications","authors":"D. Chamla, A. Kaiser, A. Cathelin, D. Belot","doi":"10.1109/ESSCIR.2004.1356626","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356626","url":null,"abstract":"This paper presents a tunable 50 kHz-2 MHz 3/sup rd/-order lowpass Butterworth Gm-C filter for use in a baseband module of a zero-IF cellular multistandard receiver, including GSM/DCS/PCS and W-CDMA, designed and fabricated in a 0.25 /spl mu/m, 2.5 V SiGe BiCMOS process. Measurements exhibit good inband linearity (up to +18 dBVp), large tuning range (>30:1), moderate noise and power consumption (1 mW to 4 mW per channel) for a silicon area of only 0.5 mm/sup 2/ (I&Q channels).","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128368291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM 5 GHz CMOS低噪声放大器，电感式ESD保护超过3kv HBM
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356676
P. Leroux, M. Steyaert
{"title":"A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM","authors":"P. Leroux, M. Steyaert","doi":"10.1109/ESSCIR.2004.1356676","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356676","url":null,"abstract":"This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 /spl mu/m CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication 一种具有空间卷积编码器的高效节能4-PAM信令方案，用于片对片通信
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356681
K. Farzan, D. Johns
{"title":"A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication","authors":"K. Farzan, D. Johns","doi":"10.1109/ESSCIR.2004.1356681","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356681","url":null,"abstract":"Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed which can achieve 3-5 dB coding gain over uncoded 4-level pulse amplitude modulation (PAM). The receiver for this signaling scheme, along with a regular 4-PAM receiver, was designed and implemented in a 0.18 /spl mu/m standard digital CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. The entire receiver for this scheme consumes only 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm/sup 2/.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifier 采用电流放大器的低功耗高线性2.4 GHz CMOS接收器前端
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356710
I. Kwon, Kwyro Lee
{"title":"A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifier","authors":"I. Kwon, Kwyro Lee","doi":"10.1109/ESSCIR.2004.1356710","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356710","url":null,"abstract":"A low power 2.4 GHz CMOS receiver front end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using a current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18 /spl mu/m CMOS technology and IIP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS 低功耗14位电流转向DAC，适用于0.13/spl mu/m CMOS的ADSL2+/CO应用
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356643
Dario Giotta, P. Pessl, M. Clara, Wolfgang Klatzer, R. Gaggl
{"title":"Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS","authors":"Dario Giotta, P. Pessl, M. Clara, Wolfgang Klatzer, R. Gaggl","doi":"10.1109/ESSCIR.2004.1356643","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356643","url":null,"abstract":"This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122668686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Design of a highly integrated tuner suitable for analog and digital TV systems 一种适用于模拟和数字电视系统的高度集成调谐器的设计
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356686
R. Berenguer, E. Hernández, N. Rodriguez, I. Cendoya, Armando Munoz, H. Solar
{"title":"Design of a highly integrated tuner suitable for analog and digital TV systems","authors":"R. Berenguer, E. Hernández, N. Rodriguez, I. Cendoya, Armando Munoz, H. Solar","doi":"10.1109/ESSCIR.2004.1356686","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356686","url":null,"abstract":"This paper presents the design of a highly integrated tuner suitable for analog and digital terrestrial TV applications. The tuner system implements an additional up-conversion stage, which allows allocation of any TV channel at IF to the terrestrial TV frequency band (47-860 MHz). This way, applications of conventional tuner systems are expanded. Results based on standard tests have shown that the designed tuner is able to deliver the necessary performance in terms of selectivity, <-35 dB to adjacent channel protection ratio, SNR of 54 dB, in band spurious emissions lower than 60 dBc and /spl Delta/IMD/sub 3/ of 52.8 dB worst case. Finally it has been also demonstrated that with a careful design of the analog components (mixers and oscillators) the restrictive specifications of the TV tuner can be fulfilled by implementing the tuner in a low-cost standard technology (0.8 /spl mu/m SiGe). The total power consumption of the complete tuner is around 390 mA from a 5 V power supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A small ripple regulated charge pump with automatic pumping control schemes 具有自动泵浦控制方案的小脉动调节电荷泵
Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI: 10.1109/ESSCIR.2004.1356698
Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Jae-Youl Lee, H. Yoo
{"title":"A small ripple regulated charge pump with automatic pumping control schemes","authors":"Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Jae-Youl Lee, H. Yoo","doi":"10.1109/ESSCIR.2004.1356698","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356698","url":null,"abstract":"Two schemes for a charge pump are presented, to reduce output ripple voltage, with high load current drivability. The first is an automatic pumping current control scheme which automatically adjusts the size of the pumping driver to reduce the ripple voltage. The second is an automatic pumping frequency control scheme, which changes the pumping period by controlling a VCO. The prototype chip provides 30-mA load current and delivers a regulated 4.5-V output with a flying capacitor of 330-nF and a clock frequency which automatically varies from 400-kHz to 600-kHz at a 3.3-V supply. The area is 0.25 mm/sup 2/ in a 3.3-V 0.13-/spl mu/m CMOS technology, and measured output ripple voltage is less than 33.8-mV with 2-/spl mu/F load capacitor. Power efficiency is higher than 70%.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126173511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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