{"title":"5 GHz CMOS低噪声放大器,电感式ESD保护超过3kv HBM","authors":"P. Leroux, M. Steyaert","doi":"10.1109/ESSCIR.2004.1356676","DOIUrl":null,"url":null,"abstract":"This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 /spl mu/m CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM\",\"authors\":\"P. Leroux, M. Steyaert\",\"doi\":\"10.1109/ESSCIR.2004.1356676\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 /spl mu/m CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356676\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM
This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 /spl mu/m CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.