A low-power clock generator for system-on-a-chip (SoC) processors

Abstract

This paper describes a low-power, low-jitter clock generator for system-on-a-chip (SoC) processors. Low-jitter is achieved by using a ROM-less direct digital synthesizer with analog phase interpolation. Low-power is achieved by using differential and feedback replica bias circuit topologies. A 6-bit resolution prototype is implemented in 0.25 /spl mu/m CMOS technology. Results demonstrate that the clock generator's area is 0.12 mm/sup 2/ and consumes only 1.5 mA of current consumption at 2.5 V. In comparison with other similar state-of-the-art implementations, this represents savings of 37.5/spl times/ and 5.87/spl times/ in area and power consumption, respectively.