{"title":"L1/L2双频CMOS GPS接收机","authors":"Jongmoon Kim, Sang-Bock Cho, J. Ko","doi":"10.1109/ESSCIR.2004.1356624","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"L1/L2 dual-band CMOS GPS receiver\",\"authors\":\"Jongmoon Kim, Sang-Bock Cho, J. Ko\",\"doi\":\"10.1109/ESSCIR.2004.1356624\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356624\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356624","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 /spl mu/m CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.
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