H. Hahn, B. Reuters, S. Kotzea, G. Lukens, S. Geipel, H. Kalisch, A. Vescan
{"title":"First monolithic integration of GaN-based enhancement mode n-channel and p-channel heterostructure field effect transistors","authors":"H. Hahn, B. Reuters, S. Kotzea, G. Lukens, S. Geipel, H. Kalisch, A. Vescan","doi":"10.1109/DRC.2014.6872396","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872396","url":null,"abstract":"GaN-based devices have shown to be promising alternatives to Si-based devices in a wide range of applications. After covering several frequency bands in RF power amplification, GaN-based devices also penetrate into the power-switching market. Owing to the high carrier density and the high mobility in a 2-D electron gas (2DEG) and a large bandgap, GaN-based devices have shown great performance. These properties may also be exploited in digital logic applications, for which complementary logic offers the lowest power consumption. Hence, p-channel devices which employ a 2-D hole gas (2DHG) have attracted increasing research interest lately [1,2]. The recent progress of p-channel device characteristics [1] finally enables the monolithic integration of p- and n-channel transistors. Hence, complementary logic on basis of GaN (C-GaN) is within reach. As a first step towards C-GaN, the first report on the integration of enhancement mode (e-mode) n- and p-channel devices on a single wafer is presented. Challenges encountered are discussed and a first voltage transfer characteristic of an inverter structure is shown.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125636620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Chabak, Xin Miao, Chen Zhang, D. Walker, Xiuling Li
{"title":"RF performance of 3D III-V nanowire T-Gate HEMTs grown by VLS method","authors":"K. Chabak, Xin Miao, Chen Zhang, D. Walker, Xiuling Li","doi":"10.1109/DRC.2014.6872372","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872372","url":null,"abstract":"Continued down-scaling of digital and RF electronics has spawn new research efforts in various nanotechnologies such as 2D semiconducting sheets and nanowires as the conducting transistor channel. Nanoscale field-effect transistors (FETs) promise to bring power-efficient operation, improved short channel effects, and added functionalities beyond conventional top-down planar devices such as facile heterogeneous integration. So far, impressive results with fT > 400 GHz have been achieved with graphene FETs [1]. However, the highest achieved fmax for carbon-based devices is below 70 GHz [2] which is related to poor output conductance (gds) and weak channel modulation either from metallic carbon nanotubes or a metallic-like gapless graphene channel. While a high fT is important, FETs generally benefit from fmax > fT for amplification of RF signals [3]. III-V nanowires (NWs), on the other hand, retain well-known transport characteristics with inherent 3D profile for improved electrostatics. The most commonly used growth method for NWs is via the metal-assisted vapor-liquid-solid (VLS) mechanism. Several III-V NW FETs have been reported with excellent dc performance, but preference for NW growth to proceed normal to the substrate has stunted RF devices where arrays of NW channels are required to deliver sufficiently high raw current. Vertical InAs NW FETs have been reported with impressive 100+ GHz performance, but remain limited by challenging device fabrication and parasitic overlapping pad capacitance [4,5]. Both of these limitations can be avoided by growing high-density NW arrays along the surface of the substrate. Here, we present the first demonstration of VLS grown III-V NW channels self-assembled in parallel arrays with fT/fmax > 30/70+ GHz using a GaAs channel. These results are state-of-the-art for III-V NWs assembled in planar arrays.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wenchao Lu, Wenbo Chen, Yibo Li, Prem Thapaliya, R. Jha
{"title":"ReRAM device performance study with Transition Metal Disulfide interfacial layer","authors":"Wenchao Lu, Wenbo Chen, Yibo Li, Prem Thapaliya, R. Jha","doi":"10.1109/DRC.2014.6872342","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872342","url":null,"abstract":"Transition Metal Oxide (TMO) based resistive random access memory (ReRAM) devices have been a topic of extensive research in the recent years [1]. However, in spite of significant research progress in this area, there are several pending issues that need to be studied. Of these several issues, two of the major issues lie in reducing the electroforming (EF) voltage, and reset current in the current state of the art ReRAM devices. To address these issues, we investigated the impact of inserting an ultra-thin interfacial layer (IL) of Transition Metal Disulfide (TMD) based on WS2 on the switching characteristics of HfO2 based ReRAM devices. Our studies indicated that the incorporation of WS2 IL resulted in a significant reduction in the EF voltage and reset current compared to the control devices. This observation indicates the possibility of achieving low-switching energy ReRAM devices by optimization of TMO/TMD interface and thicknesses.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Room temperature negative differential resistance in a GaN-based Tunneling Hot Electron Transistor","authors":"Z. C. Yang, D. Nath, S. Rajan","doi":"10.1109/DRC.2014.6872343","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872343","url":null,"abstract":"In this work, we use ballistic quantum transport in a III-nitride to realize room temperature negative differential resistance (NDR) in a GaN-based Tunneling Hot Electron Transistor. The results showed reproducible double-sweep characteristics, with peak-to-valley ratio (PVCR) of 7.2 and peak current density (PCD) about 143 A/cm2. This is the first report of repeatable room temperature negative differential resistance in a III-nitride device.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132774878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Yalon, D. Kalaev, A. Gavrilov, S. Cohen, I. Riess, D. Ritter
{"title":"Detection of the conductive filament growth direction in resistive memories","authors":"E. Yalon, D. Kalaev, A. Gavrilov, S. Cohen, I. Riess, D. Ritter","doi":"10.1109/DRC.2014.6872415","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872415","url":null,"abstract":"Resistive switching random access memory (RRAM) is among the leading future non-volatile memory technologies; however, its implementation is hampered by the lack of full understanding of the switching and conduction mechanism as well as the lack of detailed physical models [1]. In particular, there are conflicting reports in the literature on the direction of growth of conductive filaments in valence change memories (VCM). Filament growth is a key aspect in the operation of bipolar RRAM devices as it determines the polarity of the device as well as the “active” switching location. In some cases, it was shown directly by electron microscopy that filaments grow from the cathode towards the anode during forming, as in typical electrochemical metallization (ECM) cells [2]. In other cases, it was concluded indirectly that filaments originate from the anode [3]. Electron microscopy of filaments is highly challenging, and reports are scarce. Here, we show that the metal-insulator-semiconductor bipolar transistor structure can be used to detect the direction of growth of the conductive filament, and apply this procedure to validate our model of the dynamics of filament growth [4].","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133838220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Teran, M. Dejarld, Jinyoung Hwang, Wootaek Lim, Joeson Wong, D. Blaauw, Yoonmyung Lee, J. Millunchick, J. Phillips
{"title":"Indoor photovoltaic energy harvesting for mm-scale systems","authors":"A. Teran, M. Dejarld, Jinyoung Hwang, Wootaek Lim, Joeson Wong, D. Blaauw, Yoonmyung Lee, J. Millunchick, J. Phillips","doi":"10.1109/DRC.2014.6872392","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872392","url":null,"abstract":"Low power electronic circuitry, including wirelessly interconnected sensor nodes, is a transformational technology that can be applied to a broad range of applications. These low power systems still require electrical power, ideally from ambient energy sources. Ambient sources of light can provide sufficient energy for these applications. Stray sunlight is more than adequate, though it is not available in all locations. Indoor lighting may also provide a sufficient energy source, though the characteristics of the spectrum are significantly different than the solar spectrum, where irradiance is confined to a narrower window in the visible spectrum. Energy-autonomous operation in mm-scale sensors have been achieved using photovoltaics based on silicon CMOS [1,2]. Improvements in energy harvesting are necessary to increase the duty cycle of the microsystem and to facilitate wireless transceivers. Photovoltaic cells consisting of materials with larger bandgap energy, such as GaAs, provide a better match to the indoor light spectrum, reducing thermalization losses and increasing power generation. The larger voltage provided by higher bandgap materials such as GaAs can also improve the efficiency of the overall system, where higher voltages are beneficial for the battery storage system and DC-DC converter. While the cost of GaAs photovoltaics is significantly higher than for silicon, and is currently prohibitive for large area solar energy production, the small power requirements and associated size requirements for photovoltaic cells makes GaAs an affordable option. Requirements for active and standby power are 10μW and 0.5nW, respectively[1,2], where perpetual operation may be achieved using a photovoltaic cell with area on the order of 1 mm2.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Critical binding energy for exciton dissociation and its implications for the thermodynamic limit of organic photovoltaics","authors":"M. Khan, M. Alam","doi":"10.1109/DRC.2014.6872406","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872406","url":null,"abstract":"Spectroscopic signatures of strongly bound excitons (binding energy, E<sub>B</sub>) in various low dielectric constant materials and reduced dimensional systems, such as CNT transistors, Quantum well lasers, etc. are often erased during room temperature, high-field, high-power-density operation of these devices. Similarly, while pump-probe experiments have been used extensively to explore exciton dynamics in organic photovoltaics (OPVs), one wonders if the exciton bottlenecks would persist under continuous broadband illumination of OPV. In this paper, we use a self-consistent thermodynamic model (involving detailed-balance and energy-conservation) to explicitly model the kinetics of exciton dissociation and corresponding energy balance considerations [1,2]. We find that exciton bottleneck may arise under normal PV operation if and only if the exciton binding energy, E<sub>B</sub> > <sub>B(critical)</sub> ≡ (p<sub>therm</sub> + ΔE)× J<sub>sc</sub>/J<sub>opt</sub>, where J<sub>sc</sub> and J<sub>opt</sub> are the short-circuit and maximum power point currents, with the ratio~1; the thermalization per carrier is given by p<sub>therm</sub> ≈ P<sub>therm</sub>/(J<sub>SC</sub>) ≈ ((4+ξ+6/ξ)/(2+ξ)) kT<sub>s</sub> (for an ideal blackbody source), with ξ = E<sub>G</sub>/kT<sub>s</sub>. And, ΔE is the type-II band-discontinuity of a bulk-heterojunction (BHJ) cell. We predict that all signatures of exciton-limited performance of OPV would be eased if E<sub>B</sub> <; E<sub>B(critical)</sub>, and the operation of an OPV would be indistinguishable from their classical counterparts.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130042534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The spin switch oscillator: A new approach based on gain and feedback","authors":"V. Diep, S. Datta","doi":"10.1109/DRC.2014.6872412","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872412","url":null,"abstract":"We propose a new kind of oscillator based on incorporating feedback into a transistor-like amplifying device namely the spin switch. Unlike the present-day state-of-the-art spin transfer nano oscillators (STNO) based on the delicate balancing of magnetic fields and spin currents, this spin switch oscillator (SSO) should exhibit high tunable output power without the need of external magnetic fields.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126615556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Mandapati, S. Shrivastava, B. Das, Sushama, V. Ostwal, J. Schulze, U. Ganguly
{"title":"High performance sub-430°C epitaxial silicon PIN selector for 3D RRAM","authors":"R. Mandapati, S. Shrivastava, B. Das, Sushama, V. Ostwal, J. Schulze, U. Ganguly","doi":"10.1109/DRC.2014.6872387","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872387","url":null,"abstract":"The high performance of Si based selection devices is constrained by the high processing temperature requirement (>700°C) for 3D storage memory application. Many high performance Si based selection devices have been demonstrated. Epitaxial [1] and poly PN junction diodes [2-3] have been demonstrated for unipolar RRAM while epitaxial NPN punch-through diodes [4] has been developed for bipolar RRAM as summarized in Table 1. However, Si based selection devices require high temperature (>700°C) epitaxy, CVD, or crystallization. The main challenges for low temperature process are (i) high dopant activation for on-current density (ii) low defects for low off-current. In this paper, we demonstrate that sub-430°C temperature Si diodes by Si MBE with excellent performance. 3D stacking by various strategies e.g. lateral epitaxial overgrowth on seed hole [5], is enabled by back-end compatible temperature of epitaxy.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123722771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. D’Souza, M. Salehi-Fashami, Supriyo Bandyopadhyay, J. Atulasimha
{"title":"Hybrid spintronics-straintronic nanomagnetic logic with two-state elliptical and four-state concave magnetostrictive nanomagnets","authors":"N. D’Souza, M. Salehi-Fashami, Supriyo Bandyopadhyay, J. Atulasimha","doi":"10.1109/DRC.2014.6872321","DOIUrl":"https://doi.org/10.1109/DRC.2014.6872321","url":null,"abstract":"Recently, nanomagnetic logic has emerged as a promising alternative to transistor based logic because it offers both non-volatility and energy-efficiency. In particular, if the switching of the nanomagnets employs “straintronics” [1], whereby the magnetization of a multiferroic magnet is switched with a tiny voltage generating strain in a magnetostrictive-piezoelectric composite, the energy dissipated per bit flip can be reduced to a few hundred kT at room temperature. We had shown, in prior work, that a multiferroic nanomagnet with biaxial magnetocrystalline anisotropy has four stable magnetization orientations that can encode four states (Fig. 1a). Besides doubling the logic density (four-state versus two-state) for logic applications [2, 3], these four-state nanomagnets can be exploited for higher order applications such as image reconstruction and recognition in the presence of noise, associative memory and neuromorphic computing [4].","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}