IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献_第8页

America, Japan, and Europe-which areas have the edge in customer satisfaction and why [semiconductor capital equipment] 美国、日本和欧洲——哪些地区在客户满意度方面有优势，为什么?【半导体资本设备】

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731557

C.D. Burgeson

{"title":"America, Japan, and Europe-which areas have the edge in customer satisfaction and why [semiconductor capital equipment]","authors":"C.D. Burgeson","doi":"10.1109/ASMC.1998.731557","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731557","url":null,"abstract":"The results are in for the 1998 VLSI Research Inc. customer satisfaction survey on semiconductor capital equipment, and the overall ratings have increased by 0.10 points, to 7.28. This outcome is the effect of improved customer support and equipment performance by Japanese and American suppliers. One of the reasons for the year's enhanced effort is the lack of growth in the equipment market. Although focusing on customer satisfaction is important under any circumstances, companies often increase their attention to customers as sales decrease. As a consequence of this extra attention, the competition for customer satisfaction is increasing. For example, every year the top companies improve the previous year's score, and the top ratings in all five product categories have increased in the last two years. Another example of competition is the convergence of scores among areas of the world. In the 1996 survey, the difference in ratings between first place (European suppliers) and last (Japanese suppliers) was 0.87 points, but this difference decreased to 0.78 points in 1997. In the 1998 survey, European manufacturers still have the highest ratings and Japanese have the lowest, but the difference is now only 0.40 points. The main reason for this immense change in the past year is a surprising decline in ratings for European suppliers. This article analyses survey results for each of the three supplier groups, and looks at the reasons behind the convergence in customer satisfaction ratings.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"1651 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

In-line defect density targets for new technology from development to manufacturing 新技术从开发到制造的在线缺陷密度目标

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731548

E. Shamble, M. Ben-tzur, S. Sharifzadeh

引用次数: 0

Batch size optimization of a furnace and pre-clean area by using dynamic simulations 用动态模拟方法优化炉膛和预洁净区的批量

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731643

H. Rulkens, E.J.J. Van Campen, J. van Herk, J. Rooda

引用次数: 21

Defect inspection sampling plans-which one is right for me? 缺陷检验抽样计划-哪一个适合我?

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731415

B. Scanlan

{"title":"Defect inspection sampling plans-which one is right for me?","authors":"B. Scanlan","doi":"10.1109/ASMC.1998.731415","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731415","url":null,"abstract":"Most wafer fabrication lines now employ some form of defect inspection plan to identify killer defect types on its wafers and thus protect and predict die sort yields. Although often viewed as a nonvalue added process step, defect inspection is typically incorporated into the process flow at a number of points. However, as with all process steps, there is an associated cost, and oversampling can add more to the wafer manufacturing cost than the cost of field loss that might otherwise have been recovered. It is therefore imperative that the sampling methodology used in the fab is cost effective, i.e. that the benefits gained far outweigh inspection cost. As a minimum, the plan must be able to detect excursions that will ultimately result in probe yield loss. Also, excursion detection must be timely to ensure that the product at risk from excursions is minimized. In summary, the plan must be consistent with the acceptable excursion yield loss in the fab. This paper looks at plans used in two very different fabs on the same site. The first is a 4\" line with >1 /spl mu/m geometries. The second is a 6\" line with <0.5 /spl mu/m geometries. The same overall structure governs both fabs and the equipment set in both areas is largely similar. However, the sampling strategy used in the two areas is different, as each area plan is tailored specifically to meet its needs in relation to yield objectives. This paper describes the two plans used, and looks at how inspection sensitivity must be tailored to meet the needs of the plan. We look at various defect types, and how some must be sieved out to ensure that the inspection data generated is meaningful.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A manufacturable shallow trench isolation process for 0.18 /spl mu/m and beyond-optimization, stress reduction and electrical performance 可制造的浅沟隔离工艺为0.18 /spl mu/m及以上-优化，减少应力和电气性能

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731638

F. Nouri, O. Laparra, H. Sur, G.C. Tai, D. Pramanik, M. Manley

引用次数: 1

Statistical methods for measurement reduction in semiconductor manufacturing 半导体制造中测量减小量的统计方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731556

R. Babikian, Curt Engelhard

引用次数: 5

Performance and productivity improvements in an advanced dielectric etch reactor for sub 0.3 /spl mu/m applications 在一个先进的电介质蚀刻反应器的性能和生产力的提高，为低于0.3 /spl μ m的应用

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731639

M. Srinivasan, R. Caple, G. Hills, G. Mueller, T. Nguyen, E. Wagganer

{"title":"Performance and productivity improvements in an advanced dielectric etch reactor for sub 0.3 /spl mu/m applications","authors":"M. Srinivasan, R. Caple, G. Hills, G. Mueller, T. Nguyen, E. Wagganer","doi":"10.1109/ASMC.1998.731639","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731639","url":null,"abstract":"Dielectric film etching represents one of the most challenging aspects of semiconductor processing. At present, a dielectric etch reactor must be capable of handling a range of dielectrics, such as doped and undoped silica glass, silicon nitride, organic anti-reflection layers and low-k dielectric materials of a predominantly organic composition. Successful etch tools perform the \"critical\" steps required for contact, self-aligned contact (SAC), via and dual damascene structures as well as the less critical steps such as spacers and passivation that are required by leading edge 0.25 /spl mu/m generation devices as they enter volume production. Finally, all the etches must be cost effective as measured with the standard metrics of cost of ownership (COO), and overall equipment effectiveness (OEE). In this paper, we describe how these metrics have been used to generate several product improvement programs for an advanced dielectric reactor, the 4520XL/sub E//sup TM/ from Lam Research. Both process and productivity improvements are shown for sub-0.3 /spl mu/m feature size devices. These improvements show promise for extension of the applicability of the 4520XL/sub E/ reactor to sub-0.2 /spl mu/m feature sizes.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128844340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Better dispatch application-a success story [IC manufacture] 更好的调度应用——一个成功案例[集成电路制造]

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731632

Anke Giegandt, G. Nicholson

引用次数: 5

Novel methodology to include all measured extension values per defect to improve defect size distributions 新颖的方法，包括每个缺陷的所有测量的扩展值，以改善缺陷大小分布

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731553

C. Hess, L. Weiland

引用次数: 3

The advantages of using short cycle time manufacturing (SCM) instead of continuous flow manufacturing (CFM) 短周期制造(SCM)替代连续流制造(CFM)的优势

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731385

D. P. Martin

{"title":"The advantages of using short cycle time manufacturing (SCM) instead of continuous flow manufacturing (CFM)","authors":"D. P. Martin","doi":"10.1109/ASMC.1998.731385","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731385","url":null,"abstract":"Over the past two decades, continuous flow manufacturing (CFM) has been the principal operational tool to manage and improve manufacturing asset usage. CFM measures and manages throughput of the tools/toolsets that comprise the manufacturing line. Various systems have been proposed to help manage throughput (e.g. PUSH, PULL, theory of constraints) with their attendant control methodologies (e.g. MRP, KANBAN, drum-buffer-rope). This paper explores how the X-factor (normalized cycle time) rather than throughput is used as the prime line control and analysis parameter; hence, the name short cycle time manufacturing (SCM). As manufacturing lines have both throughput and X-factor commitments, it is essential to understand the fundamental relationships between throughput, capacity and X-factor. This paper also shows that X-factor is a much more sensitive indicator of capacity problems than throughput, as X-factor increases rapidly as throughput approaches effective capacity. This X-factor sensitivity can be used as a diagnostic tool to uncover unforeseen capacity issues. Short cycle time manufacturing (SCM) allows each tool/toolset to be analyzed depending on its demonstrated X-factor and capacity versus target to determine which tools/toolsets need improvement, as the overall X-factor of the line is just the weighted sums of the component toolset X-factors. This paper also analyzes the impact of mix and volume with a cycle time constraint on the capacity of tools that are affected by batch or train size. SCM provides significant advantages over CFM in helping to manage and improve manufacturing asset utilization.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133079740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22