IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献_第7页

Rewards, structure and alignment affect goal attainment 奖励、结构和一致性影响目标的实现

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731466

J. Gentleman-Ingersoll

引用次数: 0

In-situ gate oxide/electrode deposition for a 0.5 /spl mu/m BiCMOS process flow 0.5 /spl mu/m BiCMOS工艺流程的原位栅氧化物/电极沉积

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731549

T. A. Carbone, G. Solomon

引用次数: 1

Design for manufacturability: a key to semiconductor manufacturing excellence 可制造性设计:半导体制造卓越的关键

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731579

R. Wilcox, T. Forhan, G. Starkey, D. Turner

{"title":"Design for manufacturability: a key to semiconductor manufacturing excellence","authors":"R. Wilcox, T. Forhan, G. Starkey, D. Turner","doi":"10.1109/ASMC.1998.731579","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731579","url":null,"abstract":"This paper reviews measures of manufacturing excellence and presents a design-for-manufacturability (DFM) program organized around early design and manufacturing teamwork and the economic analysis of design options. Typical measures of manufacturing excellence for a semiconductor fabricator are expressed in terms of either operational or economic results. Those expressed in terms of operational results are independent of the product mix in the fabricator while those expressed in terms of economic results integrate both fabricator and product design attributes into a single parameter such as revenue/wafer. Improvements in the operational measures of manufacturing excellence focus upon increases in capacity and throughput, defect density reductions, and cost containment. Improvements in the economic measures of manufacturing excellence must focus on both fabricator processing efficiency and the productivity of the design. Design-for-manufacturability practices can improve design productivity, time-to-market, and product performance and reliability by closely coupling semiconductor fabrication knowledge with product requirements during the initial phase of a product design. Every design decision produces both technical and economic consequences; understanding these consequences and using this knowledge in the design process to optimize product productivity and profitability is key to achieving manufacturing excellence for that product.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Sidewall angle measurements using CD SEM 利用CD扫描电镜测量侧壁角

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731568

B. Su, T. Pan, P. Li, J. Chinn, X. Shi, M. Dusa

引用次数: 11

Highly selective oxide to nitride etch processes on BPSG/nitride/oxide structures in a MERIE etcher 在MERIE蚀刻机中对BPSG/氮化物/氧化物结构进行高选择性氧化-氮化蚀刻工艺

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731580

W. Graf, D. Basso, F. Gautier, J.M. Martin, E. Sabouret, G. Skinner

引用次数: 4

Effective defect detection and classification methodology based on integrated laser scanning inspection and automatic defect classification 基于激光扫描检测与缺陷自动分类的有效缺陷检测与分类方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731570

Y. Fan, Y. Moalem

{"title":"Effective defect detection and classification methodology based on integrated laser scanning inspection and automatic defect classification","authors":"Y. Fan, Y. Moalem","doi":"10.1109/ASMC.1998.731570","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731570","url":null,"abstract":"In-line defect monitoring in VLSI manufacturing is indispensable for yield management in the sub-0.25 /spl mu/m era. One of the most important functions of wafer inspection is to capture process excursions and identify the sources of yield-limiting (killer) defects. Wafer inspection has three stages: (1) defect detection, (2) defect review and classification, and (3) process defectivity trend analysis. This paper presents a new methodology for wafer inspection and defect classification by integrating a production-proven wafer inspection system (KLA-Tencor AIT) with a production-proven ADC (automatic defect classification) system (KLA-Tencor IMPACT ADC). The integrated system takes a cassette of wafers and automatically produces all information needed to analyze defectivity trends by type. Adding the on-board ADC system does not increase inspection system footprint, which is an important consideration in an industry where production floor space is precious. In this paper, we present results of characterization of the combined inspection/ADC system, including case studies from manufacturers. The results include: ADC accuracy and purity compared to manual classification on various process layers; overall time-to-results compared to traditional inspection/classification strategies; and defect sizing based on high resolution defect images of ADC compared with SEM measurement. Key advantages of the combined inspection/ADC system were found to include high classification accuracy and consistency, improved ability to track defectivity trends by defect type, improved overall time to results, and reduction of process excursion costs to IC manufacturers.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Management of multiple-pass constraints [IC fabrication] 多通约束管理[集成电路制造]

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731645

J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez, E. Paule, D. Ojeda

{"title":"Management of multiple-pass constraints [IC fabrication]","authors":"J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez, E. Paule, D. Ojeda","doi":"10.1109/ASMC.1998.731645","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731645","url":null,"abstract":"The theory of constraints (TOC) is becoming a new paradigm in the semiconductor industry. Most practical uses of TOC are for bottlenecks with only one visit to the fabrication process such as typical job shop linear lines. Applying TOC to constraints with multiple steps has been shown to be too complex to handle a semiconductor shop-floor. This restriction to constraints with only one visit limits TOC potential in semiconductor environments. In this paper, we present a methodology developed to allow for the use of the TOC philosophy in fab lines with more than one product flow and more than one visit to the bottleneck in each product flow. This method consists of dividing each process sequence in segments, where each segment finishes in one visit to the bottleneck and has only that single visit to the bottleneck. Once the capacity of the bottleneck is split between the visits, each segment is managed as an independent line. The method is suitable to be used in a production environment on a shift to shift basis and allows throughput optimization of real bottlenecks.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126340975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A study in the continuous improvement process: implementation of an optimized scrubber to replace TEOS backside etch post SOG etchback 持续改进过程的研究:实施一种优化的洗涤器来取代TEOS背面蚀刻后SOG蚀刻

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731574

W. Au, D. Parks, P. Esquivel

{"title":"A study in the continuous improvement process: implementation of an optimized scrubber to replace TEOS backside etch post SOG etchback","authors":"W. Au, D. Parks, P. Esquivel","doi":"10.1109/ASMC.1998.731574","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731574","url":null,"abstract":"As device features become smaller and manufacturing processes get more complicated, exploration of ways to reduce the number of process steps is gaining serious attention. This allows the manufacturing company to remain competitive within the semiconductor industry. This paper describes a continuous improvement process through the implementation of a scrubber post SOG etchback to remove TEOS backside etch. As the particle level of the wafer backside increases after SOG etchback, TEOS backside etch was done to clean the wafer backside to minimize focusing error in subsequent photolithography steps. The module involves resist coating of the wafer front side, a buffer HF oxide etch, followed by the resist ash and strip. Replacing the entire module with a backside scrub offers significant chemical cost savings, process cycle time reduction and increased sink, coater and asher capacity. Detailed descriptions of the old and new process and a comparison of particle and yield data are presented. Overall improvement in the manufacturing process is demonstrated by measures of cycle time, chemical cost, personnel efficiency, reduction in equipment purchases, and fab capacity.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116906976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A focus on cycle time-vs.-tool utilization "paradox" with material handling methodology 关注周期时间vs。-工具使用与材料处理方法的“悖论”

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731635

G. Horn, W. Podgorski

{"title":"A focus on cycle time-vs.-tool utilization \"paradox\" with material handling methodology","authors":"G. Horn, W. Podgorski","doi":"10.1109/ASMC.1998.731635","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731635","url":null,"abstract":"From large scale factory simulation, the semiconductor manufacturing process is characterized by a fixed nonlinear relationship between mean factory cycle time and overall average tool utilization. This allows selection of one parameter, which thus determines the other, for a specific factory. Although on a local level, the relationship between cycle time and tool usage is predicted via queuing theory, we find similar results for the entire large scale factory. On this scale, the relationship is paradoxical as it does not allow short mean cycle times and high average tool usage concurrently. Net improvements in factory performance can be had only by moving this relationship to a parallel curve, more favorable in the cycle time vs. tool utilization domain, which requires fundamental system changes. Emphasis on such shifts currently focuses on methodologies locally synchronizing asset use. This paper, however, considers the aggregate factory, where local asset usage is determined only by the random influence of the factory. Local assets are considered to have ideal efficiency, and thus only the stochastic factory relations determine their performance. Such external influences are WIP availability, WIP denomination and WIP rate. With this global factory view, WIP handling methodologies have a first order effect on overall performance, which promote migration from one factory characteristic curve to a higher performance one purely through material handling changes. Dynamic discrete event simulation, with 0.5 s resolution of WIP tracking, is used to find first order effects of transport methodologies on the total system.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132519503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

MOSAIC 1 product transfer using virtual flow concept MOSAIC 1产品传递采用虚拟流概念

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731646

P. Wang, S. Spivey, E. Warda, M. Bowser, B. Cosentino, E. Zabasajja, P. Shah, S. Imam, J. Keller, J. Fulton

{"title":"MOSAIC 1 product transfer using virtual flow concept","authors":"P. Wang, S. Spivey, E. Warda, M. Bowser, B. Cosentino, E. Zabasajja, P. Shah, S. Imam, J. Keller, J. Fulton","doi":"10.1109/ASMC.1998.731646","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731646","url":null,"abstract":"Financial prosperity in wafer fabrication suggests that we must consolidate assets of contiguous and mature technology wafer fabs. Many complex challenges arise in fab consolidations. With transparent results to customers being the main objective, one intricate issue is the transfer of a technology. During the 4th quarter of 1996, Motorola Bipolar-3 (BP3) experienced a significant increase in request for product, particularly MOSAIC 1 technology. The demand exceeded BP3's capacity. Since Motorola Bipolar-2 (BP2) ran similar processes and had excess capacity, it was decided to qualify the MOSAIC 1 technology in BP2. Since these two manufacturing areas do not have identical equipment and processes, it was extremely difficult to transfer and match processes and technology between these two fabs. This paper depicts a systematic approach in transferring MOSAIC 1 technology from BP3 to BP2. Novel techniques were applied that can be the framework for future transfers, which include development and use of the concept of virtual flow, and thorough documentation of the transfer. In addition, this paper provides a unique solution to the problems incurred with a particular device. The outcome, ahead of schedule, was a successful qualification of the device.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125232383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0