IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献

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Filling the technology gap through balanced joint development projects and contracted independent research providers 通过平衡的联合开发项目和签约的独立研究提供者填补技术差距

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731472

S. Runnels, F. Miceli, I. Kim, B. Easter

{"title":"Filling the technology gap through balanced joint development projects and contracted independent research providers","authors":"S. Runnels, F. Miceli, I. Kim, B. Easter","doi":"10.1109/ASMC.1998.731472","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731472","url":null,"abstract":"Over the past several years, a noticeable amount of the semiconductor manufacturing industry's overall R&D burden has shifted from chip manufacturer to equipment supplier. However, it is difficult for equipment suppliers to support the permanent dedicated research staff required to bear their increasing R&D burden. Likewise, their counterparts inside the chip manufacturer are urged to focus on current process development, integration, and efficiency issues. This shift in the R&D burden has been widely recognized in the supplier community, which has referred to it as the \"technology gap\". This paper describes one way of dealing with that technology gap. A successful joint development project (JDP) between SpeedFam Corporation and Lucent Technologies is described and used to exemplify how the R&D burden can be properly balanced by allowing each organization to focus on their core competency. Key to the success of the JDP was the use of private, independent R&D supplied under contract by Southwest Research Institute, which also helped facilitate the balance through preliminary self-funded R&D. The paper explains how issues regarding intellectual property protection and ownership were successfully resolved and briefly describes the technology produced from the project.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128667374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Risk management exercise in a wafer fab utilizing dynamic simulation 利用动态模拟的晶圆厂风险管理练习

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731464

T. Mccay, G. Depinto

{"title":"Risk management exercise in a wafer fab utilizing dynamic simulation","authors":"T. Mccay, G. Depinto","doi":"10.1109/ASMC.1998.731464","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731464","url":null,"abstract":"In the semiconductor industry, companies must be prepared to effectively respond to emergency situations that threaten employee safety and their manufacturing sites. Most emergencies are small incidents with minor impact; however, the potential human and financial loss resulting from a large scale emergency can be very great. Prior experience had shown that although the Motorola and City of Austin emergency response groups operate effectively on an independent basis, cross-group communication and coordination needed improvement. To assist with this, a large-scale, multiple emergency drill involving all groups was conducted. A forty-two member simulation team was organized to design and implement a scenario using dynamic simulation in order to make the drill as realistic as possible. A five hour drill was successfully completed without interruption to manufacturing with approximately eighty responders at eight different, simultaneous activity areas across a 245 acre campus containing five manufacturing facilities. Several opportunities to improve and refine the processes of preplanning, response, follow-up and drill implementation were identified. Annual drills of this magnitude and style will be institutionalized as part of how each group manages risk and protects their employees and other assets.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129086240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effects of photoresist foreshortening on an advanced Ti/AlCu/Ti metallurgy and W interconnect technology 光刻胶预缩对先进Ti/AlCu/Ti冶金和W互连技术的影响

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1900-01-01 DOI: 10.1109/ASMC.1998.731584

C. Whiteside, M. Rutten, H. Trombley, H. Landis, M. Boltz

{"title":"Effects of photoresist foreshortening on an advanced Ti/AlCu/Ti metallurgy and W interconnect technology","authors":"C. Whiteside, M. Rutten, H. Trombley, H. Landis, M. Boltz","doi":"10.1109/ASMC.1998.731584","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731584","url":null,"abstract":"Competitive technology ground rules for BEOL (Back end of Line) interconnects have been shrinking aggressively. Extending the life of existing tool sets and manufacturing processes for these new aggressive technologies is required to make these newer technologes cost competitive. This paper describes the early process transfer phase of a technology installation into a manufacturing. The effects of photolithography induced metal line end shortening foreshortening) can have a significant impact on the etched Ti/AlCu/Ti/TiN metal lines (Figure 1). This defect observed after metal etch is directly attributed to foreshortening of the photoresist lines. When a tungsten contact (interconnect) is not fully covered by a resist line during the metal etch and subsequent chromic phosphoric clean operation, attack of the Ti/AlCu/Ti metallurgy occurred. The metal defect resulted in test yield loss due to open metal line and high via resistance which impacted wafer final test yield. This defect was found to impact single metal to via interfaces within small via chain defect monitors which lead to serious reliability concerns due to the low level of detectability for this problem on products.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

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