IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献

New business models for standard and ASIC products in the semiconductor industry-competing on cost and time-to-market 半导体行业标准和专用集成电路产品的新商业模式——在成本和上市时间上展开竞争

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731552

R. Akella, J. Kleinknecht, J. Gillespie, B. Kim

引用次数: 0

Copper interconnect technology-new paradigms for BEOL manufacturing 铜互连技术——BEOL制造的新范式

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731586

K. Rose, R. Mangaser

引用次数: 7

Intelligent line monitor: maximum productivity through an integrated and automated line monitoring strategy 智能线路监控:通过集成和自动化的线路监控策略，最大限度地提高生产率

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731411

T. Pilon, M. Burns, V. Fischer, M. Saunders

引用次数: 1

Statistical methodology for yield enhancement via baseline reduction 通过降低基线提高产量的统计方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731402

K. Fridgeirsdottir, R. Akella, M. Li, P. McNally, S. Mittal

引用次数: 7

Yield management for development and manufacture of integrated circuits 集成电路开发和制造的成品率管理

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731555

H. Koyama, M. Inokuchi

引用次数: 0

Manufacturing and reliability improvements in metal-oxide-metal capacitors-MOMCAPs 金属-氧化物-金属电容器- momcap的制造和可靠性改进

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731550

L. Lowell

引用次数: 8

Cu CMP with orbital technology: summary of the experience 铜CMP与轨道技术:经验总结

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731619

Y. Gotkis, D. Schey, S. Alamgir, J. Yang, K. Holland

引用次数: 10

Sub-0.25-micron interconnection scaling: damascene copper versus subtractive aluminum 低于0.25微米的互连缩放:大马士革铜与减法铝

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731585

Anthony K. Stamper, T. McDevitt, S. L. Luce

{"title":"Sub-0.25-micron interconnection scaling: damascene copper versus subtractive aluminum","authors":"Anthony K. Stamper, T. McDevitt, S. L. Luce","doi":"10.1109/ASMC.1998.731585","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731585","url":null,"abstract":"Historically, the semiconductor industry has made chip speed the focus of its high performance CMOS logic development strategy. For the wires and insulators used in the back-end-of-the-line (BEOL), this has driven the industry to use damascene tungsten chemical-mechanical polish (CMP) local interconnects and vias; SiO/sub 2/-based intermetal dielectric CMP planarization; high-aspect ratio aluminum wiring; high density plasma, ozone/TEOS, or advanced spin-on glass SiO/sub 2/ intermetal dielectrics; high density plasma reactive ion etching; and excimer-laser DUV lithography. In order to achieve 0.25 /spl mu/m CMOS performance objectives, the aluminum wire and tungsten via aspect ratios have increased by about a factor of two as compared to 0.50 /spl mu/m CMOS. This aggressive reverse scaling of BEOL dimensions increases the defect and yield issues associated with the industry standard subtractive-aluminum etch process. We believe that, if subtractive-aluminum wiring is used, the additional scaling required to meet the performance targets of sub-0.25 /spl mu/m CMOS logic will result in significantly lower yields and increased manufacturing costs. Rather than attempt to drive subtractive-aluminum wiring beyond its reasonable limits, IBM has chosen to employ an additive-copper dual-damascene wiring process for its high performance sub-0.25 /spl mu/m CMOS logic technologies. In this paper, we discuss defect density, resistance variability, and capacitance variability for 0.25 /spl mu/m and 0.18 /spl mu/m CMOS generation subtractive-aluminum and damascene copper wiring.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124888727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Development of new methodology and technique to accelerate region yield improvement 开发新的方法和技术，加快区域成品率的提高

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731405

K. Wong, P. Mitchell, J. Nulty, M. Carpenter, L. Kavan, B. Jin, G. McMahon, C. Seams, J. Fewkes, A. Gordon, C. Sandstrom

引用次数: 3

Dynamic capacity modeling [IC manufacture] 动态容量建模[集成电路制造]

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731476

J. Mercier

引用次数: 0