开发新的方法和技术,加快区域成品率的提高

K. Wong, P. Mitchell, J. Nulty, M. Carpenter, L. Kavan, B. Jin, G. McMahon, C. Seams, J. Fewkes, A. Gordon, C. Sandstrom
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引用次数: 3

摘要

对区域良率的关注被证明可以将系统良率从75%提高到90%以上,从而实现新产品缺陷密度的快速学习曲线。同时驱动随机产率和系统产率的学习曲线对于加快新产品和现有产品的产率学习是非常重要的。本文展示了从模块集成问题到设备设置和能力问题的系统良率提高。已经定义了一种新的方法来观察晶圆边缘区域,并使用系统的方法来解决晶圆边缘问题,以推动良率的提高。晶圆中心的工艺变化较小,但当晶圆靠近晶圆边缘时,会出现较大的工艺变化,从而降低晶圆边缘的良率。这种良率的下降可能是由技术架构、工艺均匀性、晶圆不对中和标记对齐方案问题引起的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Development of new methodology and technique to accelerate region yield improvement
A focus on region yield is demonstrated to improve the systematic yield from 75% to the upper 90% to achieve a quick learning curve in defect density on new products. A learning curve to drive both the random and systematic yield simultaneously are important to accelerate the yield learning on new products as well as on existing products. This paper showed the systematic yield improvement from a module integration issue to an equipment set-up and capability issue. A new methodology has been defined to look at the wafer edge region, and is used to address wafer edge issues with systematic approaches to drive yield improvement. The process variability on the center of the wafer is low, but as one approaches the edge of the wafer, large process variations arise which depress the yield at the edge of the wafers. This decrease in yield can be caused by technology architecture, process uniformity, wafer misalignment and mark alignment scheme issues.
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