IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献_第2页

Advantages to point of use filtration of photoresists in reducing contamination on the wafer surface 光刻胶过滤在减少晶圆表面污染方面的优点

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731566

D. Capitanio

{"title":"Advantages to point of use filtration of photoresists in reducing contamination on the wafer surface","authors":"D. Capitanio","doi":"10.1109/ASMC.1998.731566","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731566","url":null,"abstract":"The trends toward narrower line widths in IC manufacture has placed an ever increasing burden on contamination control in every aspect of semiconductor fabrication. Point-of-use (POU) filtration of photoresists has been used to control particle contamination on the wafer surface during coating operations. The need for tighter filtration has led to the introduction of 0.05 /spl mu/m as well as the traditional 0.10 /spl mu/m membranes to control contamination during photoresist dispensing. With the introduction of tighter membranes for use in photoresist filtration, the end-user may have concerns that the photoresist may suffer some deleterious effects by undergoing filtration. This study centers on the use of 0.05 /spl mu/m and 0.10 /spl mu/m Pall Falcon(R) filters in dispensing Microposit S1813 photoresist for reduction of surface defects on the wafer surface. The results of gel permeation chromatography (GPC) on filtered and unfiltered photoresist showed no effect on the molecular weight of the photosensitive components. Viscosity and coating thickness results indicated no loss in solids that would have an effect on the viscosity and in turn the coating thickness on the wafer surface. G-line exposure demonstrated retention of photospeed, indicating no damaging effects on resin or photosensitive components. The applications of filtration to photoresist dispensing are demonstrated as a positive step to lowering contamination on the wafer surface without deleterious effects on the performance of the photoresist.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"399 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121259160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wafer line productivity optimization in a multi-technology multi-part-number fabricator 多工艺、多零件制造厂的晶圆生产线生产效率优化

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731382

D. Maynard, R. Rosner, M. Kerbaugh, R.A. Hamilton, J.R. Bentlage, C. Boye

{"title":"Wafer line productivity optimization in a multi-technology multi-part-number fabricator","authors":"D. Maynard, R. Rosner, M. Kerbaugh, R.A. Hamilton, J.R. Bentlage, C. Boye","doi":"10.1109/ASMC.1998.731382","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731382","url":null,"abstract":"Successful semiconductor manufacturing is driven by wafer-level productivity. Increasing profits by reducing manufacturing cost is a matter of optimizing the factors contributing to wafer productivity. The major wafer productivity components are chips per wafer (CPW), wafer process or fabricator yield (WPY) and wafer final test (WFT) or functional yield. CPW is the count of product chips fitting within the useable wafer surface, and is dependent upon the chip size, dicing channel (kerf) space, and wafer-field size. WPY yield is the percentage of wafers successfully exiting the line; losses include scrap for broken wafers and failed-wafer specifications. WFT yield is the percent of chips that meet all final parametric functional electrical test specifications. Thus, the total wafer level productivity (GCPW) is described by GCPW=CPW/spl middot/WPY/spl middot/WFT. IBM's Vermont fabricator is one of the few in the industry that manufactures DRAMs, SRAMs, microprocessors, ASICs, custom logic, mixed signal, and foundry products, all on the same production floor. The product portfolio spans 12 base technologies across four photolithographic generations from 0.8 /spl mu/m to 0.225 /spl mu/m, with development of 0.18 /spl mu/m. This also encompasses 40 major process flows and over 4000 active part numbers. Such staggering complexity has motivated IBM to consider all possible optimization of these productivity components. This paper describes some of the techniques that have been deployed to achieve this goal.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Effect of 300 mm wafer and small lot size on final test process efficiency and cost of LSI manufacturing system 300mm晶圆和小批量对LSI制造系统最终测试过程效率和成本的影响

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731478

K. Nakamae, A. Chikamura, H. Fujioka

引用次数: 4

How to simultaneously reduce /spl alpha/ and /spl beta/ error with SPC? A multivariate process control approach 如何同时减少/spl α /和/spl β /误差与SPC?多变量过程控制方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731373

R. Nasongkhla, J. Shanthikumar, R. Nurani, M. McIntyre

引用次数: 0

Yield analysis and data management using Yield Manager/sup TM/ 使用Yield Manager/sup TM/进行良率分析和数据管理

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731377

F. Lee, S. Smith

{"title":"Yield analysis and data management using Yield Manager/sup TM/","authors":"F. Lee, S. Smith","doi":"10.1109/ASMC.1998.731377","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731377","url":null,"abstract":"A yield management system (YMS) is an essential component in a modern wafer fab tool set. The YMS provides tools to analyze and manage process and electrical test data from process metrology, in-line inspection monitoring, and electrical test operations. The system gives near-real time access to all data required to support wafer manufacturing. Typical yield enhancement (YE) activities include in-line defect reduction, yield excursion control, failure analysis, and baseline yield analysis. Each of these activities typically focus on a specific data type and/or set of analysis techniques to enhance yield. A solution which integrates various data types and analysis techniques with a common client/server interface is key to achieving the YE support needed for world class manufacturing yields. This paper describes experiences with Knights Technology Yield Manager/sup TM/ (Knights YM) as a fab-wide data integration and analysis tool. The Knights YM system is designed around a client-server architecture, with separate servers for database management and data analysis tasks. The system provides a single interface for extraction of multiple data types generated during device fabrication and testing, and tools to visualize, analyze, and correlate this data. All database and analysis functions can be accessed remotely via any terminal, workstation, or desktop PC which support x-terminal functions. At Motorola, the Knights YM system is used to facilitate fab data collection, management, and analysis. Examples of how the Knights YM system is being used to improve analysis capability, productivity, and response time are presented as case studies.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"18 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Wet chemical cleaning for damaged layer removal inside the deep sub-micron contact hole 湿式化学清洗，用于去除深层亚微米接触孔内的损坏层

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731582

M. Miyamoto, H. Gotoh

{"title":"Wet chemical cleaning for damaged layer removal inside the deep sub-micron contact hole","authors":"M. Miyamoto, H. Gotoh","doi":"10.1109/ASMC.1998.731582","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731582","url":null,"abstract":"Wet chemical cleaning inside the deep sub-micron contact hole after reactive ion etching (RIE) and resist removal by O/sub 2/ plasma ashing was investigated systematically. By optimizing the composition of a cleaning solution, it was found that buffered hydrofluoric acid (BHF) which consists of both a low HF concentration (about 0.1 wt%) and the high NH/sub 4/F concentration (about 40 wt%) and also contains both surfactant (40-80 ppm) and hydrogen peroxide (/spl sim/5 wt%) was the most effective for the cleaning process. It was found that this cleaning solution can simultaneously remove the sidewall protecting deposition films which adhere on the contact hole sidewall, and the damaged layer which is formed on the Si substrate surface during RIE, and the native oxide film which grows on the Si surface at the contact hole base during resist mask removal after RIE. Moreover, it was found that during cleaning, the enlargement of a 0.4 /spl mu/m contact hole can be kept within 200 /spl Aring/, and micro-roughness generation at the Si surface of the contact hole base can be prevented. It was confirmed that this cleaning solution is very effective for decreased contact resistance and increased yield in the semiconductor device manufacturing process.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123214447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Correlation of ellipsonometric modeling results to observed grain structure for OPO film stacks OPO薄膜堆的椭圆形模拟结果与观测晶粒结构的相关性

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731572

T. E. Robinson

{"title":"Correlation of ellipsonometric modeling results to observed grain structure for OPO film stacks","authors":"T. E. Robinson","doi":"10.1109/ASMC.1998.731572","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731572","url":null,"abstract":"One significant, but potentially variable, parameter in the deposition and subsequent processing of polysilicon is its microstructure. The purpose of this work was to correlate the model parameters, in this case, percentage volume fraction of polysilicon phase components, generated by regression of model dispersion using the Bruggerman effective media approximation to data acquired by the spectroscopic ellipsometry technique. Several samples are prepared, consisting of SiO/sub 2//undoped poly-Si/SiO/sub 2/ film stacks in order to measure their as-deposited average grain sizes. Ellipsonometric data is obtained for the center site of each sample, which are then compared to AFM results from similar samples. Various grain geometry approximations are applied, along with the assumption that the polysilicon structure may be modeled to consist of three components; crystalline Si in a continuous amorphous Si matrix, and voids. A mathematical relationship is established between the percentage concentration of crystalline silicon and the mean grain size for the two cases of equiaxed and columnar microstructures. Results indicate good correlation with AFM measured grain sizes. Additional work is required to further demonstrate the correlation, and develop software applications to enable in-line product monitoring.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121869147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fab implementation of a system for cleaning wafers which survive wafer-breakage events 晶圆厂实施清洁晶圆的系统，使其在晶圆破碎事件中幸存下来

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731480

D. Hilscher

引用次数: 0

Quantifying impact of WIP delivery on operator schedule in semiconductor manufacturing line 量化在制品交付对半导体生产线操作员进度的影响

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731629

A.L. Findley

{"title":"Quantifying impact of WIP delivery on operator schedule in semiconductor manufacturing line","authors":"A.L. Findley","doi":"10.1109/ASMC.1998.731629","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731629","url":null,"abstract":"Operator availability is crucial to throughput and cycle time in a semiconductor manufacturing environment. It is often difficult to determine the effect of a manufacturing practice that is well established. Where there is no automated delivery, work-in-process (WIP) transfer between processing equipment consumes operator time, and the effect is not well understood. This work quantifies the time and distance that a set of production operators spent moving product or WIP. This data was difficult to acquire, and was essential in establishing knowledge of current conditions so that improvements could be proposed. An example is provided of how such difficult-to-obtain data can indeed be gathered. At times, off-the-shelf technology designed for another purpose can be useful in arriving at a solution. A bicycle cyclometer, capable of providing time, distance, and speed readings, was adapted to function on a five-inch caster. This caster was installed on a common semiconductor wafer-box delivery cart. This paper describes the data-gathering experiment in cooperation with production operators. Learning from this experiment, including installation of the cyclometer, actual data, and how it supported follow-on improvement are discussed.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129553042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On the integration of Ta/sub 2/O/sub 5/ as a gate dielectric in sub-0.18 /spl mu/m CMOS processes 在低于0.18 /spl mu/m的CMOS工艺中，Ta/sub 2/O/sub 5/作为栅极电介质的集成

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731642

T. Devoivre, C. Papadas, M. Setton, N. Sandler, L. Vallier, I. Bouras

引用次数: 0