Wafer line productivity optimization in a multi-technology multi-part-number fabricator

Abstract

Successful semiconductor manufacturing is driven by wafer-level productivity. Increasing profits by reducing manufacturing cost is a matter of optimizing the factors contributing to wafer productivity. The major wafer productivity components are chips per wafer (CPW), wafer process or fabricator yield (WPY) and wafer final test (WFT) or functional yield. CPW is the count of product chips fitting within the useable wafer surface, and is dependent upon the chip size, dicing channel (kerf) space, and wafer-field size. WPY yield is the percentage of wafers successfully exiting the line; losses include scrap for broken wafers and failed-wafer specifications. WFT yield is the percent of chips that meet all final parametric functional electrical test specifications. Thus, the total wafer level productivity (GCPW) is described by GCPW=CPW/spl middot/WPY/spl middot/WFT. IBM's Vermont fabricator is one of the few in the industry that manufactures DRAMs, SRAMs, microprocessors, ASICs, custom logic, mixed signal, and foundry products, all on the same production floor. The product portfolio spans 12 base technologies across four photolithographic generations from 0.8 /spl mu/m to 0.225 /spl mu/m, with development of 0.18 /spl mu/m. This also encompasses 40 major process flows and over 4000 active part numbers. Such staggering complexity has motivated IBM to consider all possible optimization of these productivity components. This paper describes some of the techniques that have been deployed to achieve this goal.