IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献_第6页

Overcoming the barriers to cleaning with bubble-free ozonated de-ionized water 用无气泡臭氧化去离子水克服清洗障碍

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731559

T. Bush, S. Hardwick, M.J. Wikol

引用次数: 1

Manufacturing for design: putting process control in the language of the designer 为设计而制造:用设计者的语言来控制过程

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731551

D. Potts

引用次数: 1

Reducing perfluorinated compound emissions [CVD chamber cleaning] 减少全氟化合物排放[气相沉积室清洗]

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731554

C. Hines, J. N. Pinto, R.C. Izor, T. A. Tamayo, W. J. Miller

引用次数: 1

A study of post-chemical-mechanical polish cleaning strategies 化学-机械抛光后清洗策略的研究

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731621

C. Huynh, M. Rutten, R. Cheek, H. Linde

引用次数: 5

Predictive yield modeling for reconfigurable memory circuits 可重构存储器电路的预测良率建模

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731368

D. Ciplickas, X. Li, R. Vallishayee, A. Strojwas, R. Williams, M. Renfro, R. Nurani

引用次数: 12

Sampling methodology for SEM-based defect classification: risk, cost, and benefit analysis 基于sem的缺陷分类的抽样方法:风险、成本和效益分析

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731418

R. Akella, C.-H. Lin, Prasanna R. Chitturi

引用次数: 1

Improvement of AME 8110 oxide etcher daily clean AME 8110氧化物腐蚀机日常清洁的改进

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731388

K. Welp, P. Fisher, J. Holden, P. Wang, M. Gunn, J. Franco

{"title":"Improvement of AME 8110 oxide etcher daily clean","authors":"K. Welp, P. Fisher, J. Holden, P. Wang, M. Gunn, J. Franco","doi":"10.1109/ASMC.1998.731388","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731388","url":null,"abstract":"In semiconductor manufacturing, continuously increasing production capacity to meet customer demand is a big challenge for many mature fabs. Purchasing new equipment or building additional fabrication areas are rarely the options. New ways to improve capacity using existing resources must therefore be explored. Motorola's Bipolar 3 fab has done this in the case of Applied Materials 8110 reactive ion etchers (RIE). The 8110 RIEs at Bipolar 3 were shown to be the bottleneck machines by the capacity model due to a recent production ramp. For this reason, the capacity of the 8110 RIEs needed to increase the overall equipment effectiveness of these machines was analyzed. It was found that 82% of the equipment downtime was due to system cleans. This clean was performed daily and consumed an average of 5 hours per machine per day. It was assumed that the long clean was necessary to keep equipment defectivity low. This paper describes how a new daily clean procedure was developed and implemented in a production environment to dramatically reduce the equipment downtime. The paper also describes how the new clean procedure improved the equipment defectivity performance.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130972222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overview of plasma induced damage after dry etch processing 干蚀刻处理后等离子体损伤概述

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731581

Y. Karzhavin, W. Wu

引用次数: 1

Silicon nanoelectronics: 100 nm barriers and potential solutions 硅纳米电子学:100纳米障碍和潜在的解决方案

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731641

V. Parihar, R. Singh, K. F. Poole

引用次数: 4

Towards real time fault identification in plasma etching using neural networks 基于神经网络的等离子体腐蚀故障实时识别研究

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731394

B. Zhang, G. May

{"title":"Towards real time fault identification in plasma etching using neural networks","authors":"B. Zhang, G. May","doi":"10.1109/ASMC.1998.731394","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731394","url":null,"abstract":"As the IC industry moves further into sub-/spl mu/m fabrication technology, optimal fabrication equipment utilization is essential. Timely and accurate equipment malfunction identification can be key to success. It is also desirable to predict malfunctions well in advance of actual occurrence. In this paper, we use neural nets to model time series data extracted from a three-step plasma etch process for defining active areas in a CMOS ASIC. The data consists of real-time measurements from the three-step etch process for 140,000 silicon wafers collected over a six-month period from a Drytek plasma etcher. Two types of anomalies were present in this data: (1) constant or slowly advancing time (indicating the presence of a machine fault); and (2) missing steps (indicating something unexpected happened during the etch). Data preprocessing is carried out to eliminate any data acquisition errors in the original data and to separate the total time sequence into three sub-sequences (one per etch step). A pattern recognition technique is used to determine the process step number for each record. The classification results and the prediction error demonstrate accurate determination of the etch step number from the chamber state. Dynamic neural net models are then constructed for each step. We initially focus on modeling the time series associated with chamber pressure. The time series of pressure data is modeled as a function of its previous values and the current time. We use this approach to construct time series models of the etching system pressure variations using only the initial condition and the time value as inputs.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8