Silicon nanoelectronics: 100 nm barriers and potential solutions

Abstract

From the process integration point of view, the introduction of new materials (e.g. copper conductors, high and low k dielectrics) will be the most difficult challenge for semiconductor manufacturing in 21st century. In a paradigm shift, understanding the role of defects and how they affect yield will be similarly important. Not all the defects are killer defects, and having the ability to detect the important yield-reducing defects in a particular step will be vital. In this paper, we have focused on the major issues related to defects and process integration (e.g. introduction of new materials, new processes, new tools etc.) for a new understanding of defects that can lead to the development of sub-100 nm silicon ICs. The defect reduction and yield improvement constraints require process control techniques capable of handling large amounts of defect data. In the deep sub-100 nm realm, this will force us to look for process simplification in order to reduce complex manufacturing operations.