{"title":"Human based knowledge for the probe failure pattern classification with the use of a backpropagation neural network. Application on submicron linear technologies","authors":"C. Ortega, J. Ignacio, A. Montull, E. Sobrino","doi":"10.1109/ASMC.1998.731547","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731547","url":null,"abstract":"The practical use of what is known as soft computing (neural networks, fuzzy logic, genetic algorithms, etc.) is starting to offer important advantages in several fields. In particular, in a high-cost environment like the semiconductor arena, the application of those, up to now, research techniques offers an attractive alternative to the traditional approaches of yield enhancement. For increasing wafer diameters and more compact technologies, where the effect of tiny defects produces fatal consequences, a yield enhancement strategy based on inspections requires the synergy of intelligent new tools that, on the other hand, have a fraction of cost of the current inspection machines. This new strategy is used to classify and analyse all the production of a fab in a systematic way, providing new possibilities to improve yields without penalising cycle time, cost and reaching inspection levels impossible to achieve without this new approach.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131659879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The quantitation of surface modifications in 200 and 300 mm wafer processing with an automated contact angle system","authors":"R. Carpio, D. Hudson","doi":"10.1109/ASMC.1998.731571","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731571","url":null,"abstract":"Contact angle measurement, using advanced instrumentation, is assuming an increased role in monitoring those semiconductor manufacturing processes which modify the surface characteristics of wafers. Such measurements can provide rapid, nondestructive and spatially and time resolved data in an automated mode. This information can be related to processing uniformity and can in many cases provide information on the chemical state of the surface. Illustrations are provided in the wafer cleaning, lithography, and interconnect areas. New application areas illustrated include measurement of the uniformity of UV photostabilization processes, measurement of contrast curves, and determination of receding and advancing contact angles of processed copper wafers.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114053522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Ridley, T. Grebs, J. Trost, R. Webb, M. Schuler, R.F. Longenberger, T. Fenstemacher, M. Caravaggio
{"title":"Advanced aqueous wafer cleaning in power semiconductor device manufacturing","authors":"R. Ridley, T. Grebs, J. Trost, R. Webb, M. Schuler, R.F. Longenberger, T. Fenstemacher, M. Caravaggio","doi":"10.1109/ASMC.1998.731561","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731561","url":null,"abstract":"While the standard RCA wafer cleaning technique (Kern, 1970), is still predominantly used in semiconductor device manufacturing, several potential problems with this technique have been identified, such as surface roughness, contamination, chemical and DI water cost. Also, most of the work carried out in the area of wafer cleaning has been focused on the low power IC industry, where the active area of the device lay in the top 1 or 2 /spl mu/m of the wafer. However, in the discrete power device industry, the use of lateral and vertical current flow for high current density distribution means that the entire substrate becomes part of the device active area. Therefore, metallic contamination even in the silicon bulk can severely degrade device performance. In this study, a modified RCA wafer cleaning mixture with improved megasonic energy enhancement (Schulze and Deboy, Proc. SPIE vol. 2638, pp. 234-41, 1995) and various rinsing techniques is investigated for use in high-volume power semiconductor device manufacturing. The effectiveness of the modified dilute SC-1/SC-2 procedure is demonstrated by various material, electrical and optical analysis techniques such as ELYMAT, TXRF, laser particle counting and Wright etching. The overall advanced aqueous wafer cleaning technique shows excellent contamination removal, cleaning efficiencies /spl ges/95% at 0.15 /spl mu/m, and a reduced cost of ownership.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123526213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Miraglia, P. Miller, T. Richardson, G. Blunt, C. Blouin
{"title":"Beyond cost-of-ownership: a causal methodology for costing wafer processing","authors":"S. Miraglia, P. Miller, T. Richardson, G. Blunt, C. Blouin","doi":"10.1109/ASMC.1998.731573","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731573","url":null,"abstract":"Classical cost-of-ownership data provides detailed cost data of equipment assets but does not provide wafer processing costs. Starting with a cost-of-ownership model, a wafer processing cost model was developed and validated. This cost-of-processing model provides wafer processing cost data from raw wafer through final passivation and parametric testing. This new model goes beyond classical cost-of-ownership data and captures more than just equipment costs-process, product, and fabricator costs are also captured. These costs are then causally spread to wafers via various algorithmic methodologies. In order to do this, some historical cost problems had to be addressed, such as how to properly weight equipment usage and account for dedicated equipment requirements, deal with measurement sampling, incorporate idle time and contingency, and account for different photolithographic field sizes. Output from the model was fully validated against actual spending and tied to accounting data in order to assure a full dollar capture. The model is currently being used for product costing, decision making, and cost reduction activities at the IBM Microelectronics Division Manufacturing Facility in Essex Junction, Vermont.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121238792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R.G. Cosway, K.B. Catmull, J. Shray, R. Naujokaitis, M. Peters, D. Grant, G. Horner, B. Letherer
{"title":"Uses of corona oxide silicon (COS) measurements for diffusion process monitoring and troubleshooting","authors":"R.G. Cosway, K.B. Catmull, J. Shray, R. Naujokaitis, M. Peters, D. Grant, G. Horner, B. Letherer","doi":"10.1109/ASMC.1998.731569","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731569","url":null,"abstract":"The dynamic nature of modern semiconductor fabrication facilities requires metrology tools that can be used to diagnose infrequent problems. However, due to the high cost of clean room floor space, these tools should also provide routine monitoring capability and be able to diagnose numerous issues. For a diffusion area, the corona oxide silicon (COS) measurement technique lends itself well to double duty as both an engineering and production tool.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation analysis of 300 mm intrabay automation vehicle capacity alternatives","authors":"G. Mackulak, F. P. Lawrence, J. Rayter","doi":"10.1109/ASMC.1998.731644","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731644","url":null,"abstract":"The next generation of semiconductor manufacturing (300 mm) will need to rely on automated material handling equipment for production lot delivery within as well as between bays. This reliance is required for reliability, cleanliness, performance, cost, and ergonomic considerations. Traditional interbay movement systems have achieved exceptional performance by carrying primarily single product lots. Multi-capacity vehicles offer production facilities more advanced capabilities. They have the ability to mix lots during delivery or pick-up, operating much the same as a postman. This paper investigates the relationship between vehicle carrying capacity and process tool batch size by experimenting with a simulation model of the diffusion process. Results indicate that vehicle capacity is the most significant factor affecting average delivery time.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125412537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Foster, D. Meyersdorf, J. M. Padillo, R. Brenner
{"title":"Simulation of test wafer consumption in a semiconductor facility","authors":"B. Foster, D. Meyersdorf, J. M. Padillo, R. Brenner","doi":"10.1109/ASMC.1998.731576","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731576","url":null,"abstract":"A discrete event simulation methodology was developed to assist in managing test wafer usage in semiconductor fabs. The purpose of modeling test wafer usage is to predict the number of new test wafers required, test wafer WIP levels, and how to downgrade test wafers to reduce costs of purchasing new test wafers. The test wafer simulation methodology is a detailed yet accurate way to predict test wafer consumption. The methodology has been implemented in a 200 mm development facility, resulting in considerable cost savings by reducing the overall WIP levels of test wafers.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A comparison of critical area analysis tools [IC yield]","authors":"S. Fitzpatrick, G. O'Donoghue, G. Cheek","doi":"10.1109/ASMC.1998.731381","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731381","url":null,"abstract":"The application of critical area analysis has become more mainstream in the semiconductor industry. The critical area of a circuit is a measure of the sensitivity of a product layout to defects, which is subsequently used in accurate yield models. Intuitively, if a circuit is more dense, the defect sensitivity is higher than a less dense circuit. Commercial tools have only recently become available to measure critical area. Several approaches have been developed to measure layout critical area. A short summary of each approach is described, as well as a brief description of how critical area is incorporated into a yield model. The results of applying critical area analysis tools are then described.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122001707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Process control and monitoring with laser interferometry based endpoint detection in chemical mechanical planarization","authors":"D. A. Chan, B. Swedek, A. Wiswesser, M. Birang","doi":"10.1109/ASMC.1998.731624","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731624","url":null,"abstract":"First, a brief presentation of the principles behind laser interferometry based in-situ endpoint detection is made, including the underlying theory of operation, system architecture and filtering methodology. This is followed by experimental data taken with various process wafers, including tungsten, copper, blanket oxide, silicon-on-oxide, shallow trench isolation (STI), and interlayer dielectric (ILD) wafers. Pre- and post-processing thickness data and removal rates are compared with ex-situ measurements for accuracy and repeatability. Finally, specific examples are discussed to show the benefits of in-situ removal rate monitoring and endpoint detection in chemical mechanical planarization for improved line monitoring and process control.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114460920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correlation of digital image metrics to production ADC matching performance","authors":"J. Blais, V. Fischer, Y. Moalem, M. Saunders","doi":"10.1109/ASMC.1998.731407","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731407","url":null,"abstract":"Automatic defect classification tool matching requires that consistent quality images are captured on all tools. Image metrics have been developed and the variance of these metrics have been correlated to classifier matching. It is shown that in order to maintain tool matching, image color balance, focus, and shadowing must be monitored and maintained at acceptable values. Of these metrics, inappropriate color balance has the greatest effect on matching.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}