IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)最新文献_第4页

Automated lot tracking and identification system 自动批量跟踪和识别系统

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731473

U. Rohrer

{"title":"Automated lot tracking and identification system","authors":"U. Rohrer","doi":"10.1109/ASMC.1998.731473","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731473","url":null,"abstract":"Exactly meeting agreed delivery dates and product volumes is an essential part of the relationship between semiconductor manufacturers and their customers. In the ASIC business in particular, with a multitude of part numbers and small lot sizes, this has become a major \"customer satisfaction\" criterion. Worldwide competition is the driving force to reduce manufacturing cycle time, especially for design verification or product qualification using express lots. To supply these high priority lots in the least possible time to the proper manufacturing equipment is a critical factor in achieving short overall cycle times. In a clean room with chase-and-bay design, many different lot storage locations are distributed throughout the fab, and since logical and physical lot location can substantially differ, manufacturing operators may spend a considerable amount of time searching for the next scheduled lot for processing. The purpose of an automated global lot tracking system is aimed at giving the manufacturing operator the ability to locate any requested lot at any time anywhere in the fab; SMST therefore labeled this project Find Lot System (FiLS). It supports true \"pull mode\" for production personnel, cuts down on cycle time, thus allowing for faster yield ramp-up, decreases lot mixing and misprocessing, and helps meet targeted delivery dates. The lot tracking system installed in the SMST fab had to be adapted to the existing lot transportation system, with both SMIF pods and conventional wafer boxes, and had to be integrated into the existing manufacturing execution system (MES).","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128001983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A layer-based layout approach for semiconductor fabrication facilities 一种基于层的半导体制造设备布局方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731626

Chien-Fu Chang, Simon Chang

{"title":"A layer-based layout approach for semiconductor fabrication facilities","authors":"Chien-Fu Chang, Simon Chang","doi":"10.1109/ASMC.1998.731626","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731626","url":null,"abstract":"Most current semiconductor manufacturing fabrication facilities and those being designed for the future use a bay or process layout configuration. In this approach, the facilities are divided into a number of bays that contain processing equipment. This process layout creates a large amount of material flows between bays. While there may be other, perhaps more efficient layout arrangement strategies, the semiconductor industry is reluctant to adopt these strategies since the bay configuration offers many advantages in terms of maintenance and operation of the physical equipment. In the near future, however, the layout problem of a 300 mm semiconductor wafer fab may pay more attention to material handling than to these advantages due to 300 mm wafer size, weight, and cost issues. The effect on cycle time and WIP level of wafer must be considered especially for the layout of a 300 mm wafer fab. Adopting the idea of group technology (GT) layout, this paper proposes a layer-based approach for solving the fab facility layout problem. This approach groups the equipment of continuous process layers in the same area or cell. The continuous layer groups consist of processing layers with their process steps in sequence. The cell configuration is sequentially determined by the major process flows, and the arrangement of the machines within each cell is a flow-line layout such that the whole process steps of a layer can be done within a cell. An evaluation for layer-based layout in a sample manufacturing environment is demonstrated. Results show the efficiency and effectiveness of the layer-based layout approach.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"56 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120986071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Matching automated CD SEMs in multiple manufacturing environments 在多个制造环境中匹配自动化CD sme

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731567

J. Allgair, D. Ruehle, J. Miller, R. Elliot

{"title":"Matching automated CD SEMs in multiple manufacturing environments","authors":"J. Allgair, D. Ruehle, J. Miller, R. Elliot","doi":"10.1109/ASMC.1998.731567","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731567","url":null,"abstract":"Increasingly stringent critical dimension design rules for semiconductor manufacturing have driven manufacturers of automated CD SEMs to develop systems with improved line width measurement repeatability and reproducibility (Allgair et al., 1998). However, in a multiple tool manufacturing environment, the technical performance of CD SEMs is as much a function of consistent and tight operational controls as it is a function of the fundamental capability of the system. Efficient and strict methods for the characterization and monitoring of the measurement performance of the systems, and in particular system matching, are required to preserve proper operation. We describe a practical CD SEM control procedure, using a standard daily monitor wafer that tracks the major system components that affect CD SEM performance. A statistical analysis of this monitor data is presented which allows system matching to be verified immediately rather than requiring tests that span several days. This procedure tracks tool stability, provides a common CD SEM length reference, and enables the seamless use of multiple CD SEMs within a single manufacturing environment or between separate manufacturing environments, without significantly increasing the tool qualification time. Critical matching of six automated CD SEMs in two separate manufacturing environments is demonstrated using this technique on a variety of layers.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"25 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124308087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Improvement of silicon wafer minority carrier lifetime through the implementation of a pre-thermal donor anneal cleaning process 通过实施预热供体退火清洗工艺改善硅片少数载流子寿命

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731578

L. Martines, C. Wang, T. Hardenburger, N. Barker, B. Sohmers

{"title":"Improvement of silicon wafer minority carrier lifetime through the implementation of a pre-thermal donor anneal cleaning process","authors":"L. Martines, C. Wang, T. Hardenburger, N. Barker, B. Sohmers","doi":"10.1109/ASMC.1998.731578","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731578","url":null,"abstract":"In order to accomodate ever smaller device geometries, Si wafer quality requirements have become increasingly stringent. Si wafer minority carrier lifetime or diffusion length has become a routinely required parameter. It is well known that, in addition to crystal growth, metal contamination is a major limiting factor for Si wafer minority carrier lifetime. Optimization of the Si wafer manufacturing process flow is critical for minimization of metal contamination sources during processing. In the past, we have learned from device manufacturers that low device yields have been directly related to poor minority carrier lifetimes, or low diffusion lengths. In this paper, we show that, without a pre-thermal donor anneal cleaning process, the minority carrier lifetimes in CZ Si wafers could be degraded due to Fe incorporation during the thermal donor anneal (TDA) process. The TDA process eliminates the impact of oxygen-related thermal donor defects on wafer resistivity. Typically, the TDA process is carried out at relatively low temperatures, typically /spl sim/650/spl deg/C for 20-30 minutes. Due to the low Fe solubility in Si at this temperature, less attention was paid to the Si wafer surface conditions, mainly metal contamination levels, prior to the TDA process. However, in this paper, we show that the TDA process, even at 650/spl deg/C, has significant impact on minority carrier lifetime. In order to maintain the lifetime value at the \"crystal\" level, it is critical to implement an effective cleaning process to remove metal contamination from the Si wafer surface prior to TDA processing.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115417484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A study of boron doping profile control for a low V/sub t/ device used in the advanced low power, high speed mixed-signal IC 先进低功率高速混合信号集成电路中低V/sub /器件的硼掺杂分布控制研究

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731640

A. Chen, K. Flessner, P. Sana, R. Dixon, F. Malone, P. Ying, L. Hutter

引用次数: 2

A cost benefit analysis of photolithography and metrology dedication in a metrology constrained multipart number fabricator 在计量受限的多零件制造厂中，光刻和计量专用的成本效益分析

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731475

R. Woods

{"title":"A cost benefit analysis of photolithography and metrology dedication in a metrology constrained multipart number fabricator","authors":"R. Woods","doi":"10.1109/ASMC.1998.731475","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731475","url":null,"abstract":"Dedication in photolithography provides better process control and accurate data collection while driving reductions in both rework and process defects. The trade-off, however, is the limitation it places on the manufacturing system by restricting the number of servers where a given lot can be directed. Relaxing dedication and deployment allows for a lower cycle time through the process step, but this same relaxation may also drive the need for additional processing and measurement processing in the photolithography sector, thus encouraging longer overall cycle time for the sector. This paper analyzes the costs and benefits of dedication on the basis of overall photosector cycle time. The variables controlled by the decisions to dedicate include send-aheads, number of measurements, sample size, and skip-plan levels. Strict photolithography dedication drives fewer send-aheads, measurements, a smaller sample size and larger skip plans; a level is reached where the dedication is offset by additional waiting time for dedicated lots at specific photolithography tools. The same level of rework and process defects can be achieved at a lower overall sector cycle time by determining the minimum cycle time while maintaining the same operating procedures and quality controls. The solution, in this instance, depends on the number of technologies and part numbers being run through the photolithography sector, an effect that must be detailed and analyzed.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Semiconductor metrics: conflicting goals or increasing opportunities? 半导体指标:目标冲突还是机会增加?

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731391

L. Sattler, R. Schlueter

引用次数: 19

Control methods for the chemical-mechanical polishing process in shallow trench isolation 浅沟隔离中化学机械抛光过程的控制方法

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731396

Y. Wu, J. Gilhooly, B. Philips

引用次数: 3

Development of a production worthy copper CMP process 开发一种具有生产价值的铜CMP工艺

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731616

K. Wijekoon, S. Mishra, S. Tsai, Kumar Puntambekar, M. Chandrachood, F. Redeker, R. Tolles, B. Sun, L. Chen, T. Pan, P. Li, S. Nanjangud, G. Amico, J. Hawkins, T. Myers, R. Kistler, V. Brusic, S. Wang, I. Cherian, L. Knowles, C. Schmidt, C. Baker

引用次数: 9

Development and implementation of an automated wafer transport system 开发和实施自动化晶圆输送系统

IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168) Pub Date : 1998-09-23 DOI: 10.1109/ASMC.1998.731633

J. Sikich

{"title":"Development and implementation of an automated wafer transport system","authors":"J. Sikich","doi":"10.1109/ASMC.1998.731633","DOIUrl":"https://doi.org/10.1109/ASMC.1998.731633","url":null,"abstract":"The move to 300 mm wafers has prompted IC manufacturers to demand a reliable automated material handling system (AMHS). Hewlett Packard's Inkjet Supplies Business Unit has worked with a supplier to develop a system using overhead rails and vehicles with hoist mechanisms to perform direct-to-tool delivery of 200 mm podded wafers. The system is intended to increase throughput by providing just-in-time material delivery and improve safety by minimizing manual handling. The system has a near zero footprint, leaving valuable floor space for process tools. While the system was built specifically for 200 mm material, most of this effort is directly applicable to 300 mm systems, and tests on the new system are very promising. Tool-to-tool delivery time was approximately 38 s, and pod placement accuracy was satisfactory regardless of pod load or vertical hoisting distance. Long term reliability tests indicated mean cycles between interrupts (MCBI) per vehicle of approximately 3,286 cycles (where a cycle is a pod move from between tools). All but one of the incidents encountered during reliability testing were recovered in 1 minute or less. A third party failure mode analysis identified a small number of potential safety hazards, which the supplier is addressing. Our study also identified issues to be addressed prior to production implementation, including improved vehicle maintenance procedures and better methods of identifying, troubleshooting and resolving system errors. Further modeling and scenario testing may need to be performed to better estimate system benefits and potential integration issues for specific applications.","PeriodicalId":290016,"journal":{"name":"IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134114032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5