Simulation of test wafer consumption in a semiconductor facility

Abstract

A discrete event simulation methodology was developed to assist in managing test wafer usage in semiconductor fabs. The purpose of modeling test wafer usage is to predict the number of new test wafers required, test wafer WIP levels, and how to downgrade test wafers to reduce costs of purchasing new test wafers. The test wafer simulation methodology is a detailed yet accurate way to predict test wafer consumption. The methodology has been implemented in a 200 mm development facility, resulting in considerable cost savings by reducing the overall WIP levels of test wafers.