2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献_第7页

Linear Filters for Image Energy 用于图像能量的线性滤波器

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885178

Jian-ao Lian

引用次数: 0

Analysis of Charge Reuse in Switched-Capacitor Power-Converter Drivers 开关电容功率变换器驱动中电荷复用分析

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884823

Mark Lipski, S. Gregori

引用次数: 1

Driving Point Loop Gain and Return Ratio 驱动点回路增益和返回比

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884926

A. Ochoa, Donnie Patterson, M. McGuckin

引用次数: 5

A Low-Latency 16-Phase Pulse Width Modulator with Phase Angle Control for 140MHz Fully Integrated Voltage Regulators on 22nm Tri-Gate CMOS 低延迟16相脉宽调制器与相角控制140MHz完全集成电压调节器在22nm三门CMOS

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885345

G. Schrom, Sarath Makala, Ravi Sankar Vunnam, R. Narayanan, F. Paillet

引用次数: 1

39fJ Analog Artificial Neural Network for Breast Cancer Classification in 65nm CMOS 39fJ基于65nm CMOS的乳腺癌分类模拟人工神经网络

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885149

Ruobing Hua, A. Sanyal

引用次数: 1

Efficient calibration for robust indoor localization based on low-cost BLE sensors 基于低成本BLE传感器的鲁棒室内定位的有效校准

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885056

Nizam Kuxdorf-Alkirata, Gerrit Maus, D. Brückmann

引用次数: 6

Variable Fast Transient Digitizer 可变快速瞬态数字化仪

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885189

J. K. Mellott, E. Monahan, V. Vinayaka, Sachin P. Namboodiri, Angsuman Roy, R. J. Baker

{"title":"Variable Fast Transient Digitizer","authors":"J. K. Mellott, E. Monahan, V. Vinayaka, Sachin P. Namboodiri, Angsuman Roy, R. J. Baker","doi":"10.1109/MWSCAS.2019.8885189","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885189","url":null,"abstract":"A low cost, low power substitute for expensive, high power high-speed analog-to-digital converters (ADCs) in some situations is presented. This circuit is called a variable fast transient digitizer (VFTD). This paper provides an overview of the design and measured test results. The VFTD is designed to sample a high-speed analog input signal and later reconstruct the captured signal at a much slower rate, for example, around three orders of magnitude. This approach eliminates quantization error in the captured signal. Further, this approach enables the use of slow, low cost, analog-to-digital converters such as those found in microcontrollers. The VFTD discussed in this paper uses 256 sequential sample and hold cells with a process dependent variable delay element controlled by an off-chip voltage source. Using a power supply voltage of 5V the input range extends from 0 V to 3 V corresponding to an output voltage range from 2 V to 5 V, a capture window range from 81 ns to 1.78 µs, and a sampling rate range from 143.82 MS/s to 3.16 GS/s. The VFTD is fabricated on a 2 mm x 2 mm die using ON Semiconductor's 0.5 µm C5 process and requires a 0.5 mm x 1.5 mm area.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology 4- 40gb /s PAM-4发射机，采用65nm CMOS混合驱动技术

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885140

Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang

引用次数: 0

Improvement of Low-Light Image by Convolutional Neural Network 基于卷积神经网络的弱光图像改进

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885098

Manbae Kim

引用次数: 4

A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic 一种基于可逆逻辑的低成本可配置RO PUF设计

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885015

Bappaditya Dey, Kasem Khalil, Ashok Kumar, M. Bayoumi

{"title":"A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic","authors":"Bappaditya Dey, Kasem Khalil, Ashok Kumar, M. Bayoumi","doi":"10.1109/MWSCAS.2019.8885015","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885015","url":null,"abstract":"A Physical Unclonable Function (PUF) is a one-to-one (1:1) or a one-to-many(1:M) functional mapping operation. Given an input, which is termed as a Challenge, a PUF function produces response(s), which is termed as Response. Therefore, any PUF can be mathematically defined with its unique CRP behavior. Silicon PUFs can be implemented mainly for hardware security and thus to guarantee IP-protection. On the other side of the discussion, we are standing at the beginning of the quantum computation era, where we may start replacing all classical digital logics with the reversible logic ones. In conventional circuits, during any digital logic operation, we generally loose bits of input information (fan-in) at the output end (fan-out) and which results in unavoidable dissipation of a significant amount of energy. In reversible logic operation, we can preserve any inputoutput information bits at the input as well as output end and thus this technology can be implemented to minimize significant heat dissipation and power consumption for a fully functional physical chip while increasing the speed. The only trade-off will be designing complexity and wafer area which is our future research focus. In this paper, we propose the reversible logic design for an existing XOR Gate based Low-Cost Congurable RO PUF structure based on Feynman gate as a reversible logic block. A comparative analysis between classical and quantum logic function is also given on various parameters along with limitations of conventional computing. The proposed approach is implemented using VHDL on Xilinx-7 FPGA.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"81 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7