Analysis of Charge Reuse in Switched-Capacitor Power-Converter Drivers

Abstract

This paper presents a method of reducing the power lost when driving the gate capacitance of CMOS transistors in switched-capacitor power converters. The consequences of the increased rise and fall times on the transistor on resistance are investigated. Additionally, the effectiveness of charge reuse on the transistors of a switched-capacitor voltage doubler is simulated in 65-nm CMOS technology resulting in efficiency improvements.