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2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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A 0.045- to 2.5- GHz Frequency Synthesizer with TDC-based AFC and Phase Switching Multi-Modulus Divider 一种0.045至2.5 GHz频率合成器，具有基于tdc的AFC和相位开关多模分频器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885373
Ang Hu, Dongsheng Liu, Ke-feng Zhang, Lan-qi Liu, X. Zou
{"title":"A 0.045- to 2.5- GHz Frequency Synthesizer with TDC-based AFC and Phase Switching Multi-Modulus Divider","authors":"Ang Hu, Dongsheng Liu, Ke-feng Zhang, Lan-qi Liu, X. Zou","doi":"10.1109/MWSCAS.2019.8885373","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885373","url":null,"abstract":"A 0.045- to 2.5- GHz wideband frequency synthesizer (FS) employing time-to-digital converter (TDC) based automatic frequency calibration (AFC) method and phase switching multi-modulus divider (MMD) for quantization noise suppression is presented in this paper. The counter-based AFC method takes several reference cycles to calculate the instantaneous voltage controlled oscillator (VCO) frequency, while the proposed TDC-based technique needs only 2 cycles. In order to suppress the quantization noise caused by the sigma-delta modulator (SDM) in the MMD, the loop division step is reduced from 2 to 0.5 by adopting the phase switching (PS) technique. The FS is designed and simulated using TSMC 180nm RF CMOS process. The simulation results of the AFC time are less than 1.4 μs when employing a 48 MHz reference signal and the quantization noise is suppressed by 12 dB compared to the conventional MMD structure.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132103472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking 一种用于10gbps串行链路锁频的预倾斜双向门控延迟线Bang-Bang频率检测器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885012
Yue Li, F. Yuan
{"title":"A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking","authors":"Yue Li, F. Yuan","doi":"10.1109/MWSCAS.2019.8885012","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885012","url":null,"abstract":"This paper proposes a pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency detector (BBFD) with applications in frequency-locking of 10 Gbps (giga-bits-persecond) serial links. Bang-bang frequency detection is performed using a pair of BDGDLs that digitize the logic-1 pulse of receiver oscillator and a reference clock. A redundant successive approximation register (SAR) driven by the output of the BBFD is used to generate the frequency control word (FCW) of the digitally controlled oscillator (DCO) of the receiver. A frequency detection decision can be made in only 4 cycles of the reference clock. The frequency error of the ADFLL utilizing the proposed BBFD is analyzed. The ADFLL is designed in a TSMC 65 nm 1.2 V CMOS and tested with a 5 GHz reference clock. Simulation results show the ADFLL achieves frequency lock in less than 10 ns with the maximum frequency error in the lock state is within the frequency error boundaries of the BBFD.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An SR Flip-Flop based Physical Unclonable Functions for Hardware Security 一种基于SR触发器的硬件安全物理不可克隆功能
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885006
Rohith Prasad Challa, S. A. Islam, S. Katkoori
{"title":"An SR Flip-Flop based Physical Unclonable Functions for Hardware Security","authors":"Rohith Prasad Challa, S. A. Islam, S. Katkoori","doi":"10.1109/MWSCAS.2019.8885006","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885006","url":null,"abstract":"Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area- and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high (‘1’) and followed by logic zero (‘0’), the outputs Q and $bar Q$ can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116330171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Total Harmonic Distortion and Power Factor Improvement Technique for CRM Flyback PFC Converters CRM反激式PFC变换器的总谐波畸变及功率因数改善技术
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885187
Mustafa Kavci, A. Tekin, Cengiz Tarhan
{"title":"Total Harmonic Distortion and Power Factor Improvement Technique for CRM Flyback PFC Converters","authors":"Mustafa Kavci, A. Tekin, Cengiz Tarhan","doi":"10.1109/MWSCAS.2019.8885187","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885187","url":null,"abstract":"In many of today’s solid-state lighting applications, Critical Conduction Mode (CCM) Flyback PFC converter is a popular solution due to its limited component count and simple structure with respect to other SMPS topologies. As described in international standards documents (IEC/EN 61000-3-2), drivers are required to demonstrate a power factor results greater than 0.9 and lower THD for power levels above 25W. Due to non-sinusoidal input current waveform of the traditional constant-on-time control method, achieving improved PF and THD is quite difficult. In this paper, a new control method is introduced in an effort to improve power factor and total harmonic distortion of Voltage Mode CRM Flyback PFC Converter. The work proposes injection of a compensating sin(ωt) signal component in the feedback path utilizing an additional primary transformer winding to linearize the current from the source. The detailed theoretical analysis is presented along with measurement results of a 30W high-power system prototype.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Novel Reconfigurable Hardware Architecture of Neural Network 一种新的可重构神经网络硬件结构
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884809
Kasem Khalil, Omar Eldash, Bappaditya Dey, Ashok Kumar, M. Bayoumi
{"title":"A Novel Reconfigurable Hardware Architecture of Neural Network","authors":"Kasem Khalil, Omar Eldash, Bappaditya Dey, Ashok Kumar, M. Bayoumi","doi":"10.1109/MWSCAS.2019.8884809","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884809","url":null,"abstract":"Neural networks have been commonly used in learning applications. Implementing a neural network on hardware is a complex and challenging task for hardware designers as many hyperparameters and trade-offs need to be considered. This paper presents a reconfigurable feed-forward neural network which can be used for different applications. The proposed method has the flexibility to change the node organization to be suitable for an application. The network is divided into two parts: one part has a fixed node in each layer and the second part includes the reconfigurable nodes. The reconfigurable nodes have the ability to switch from one layer to another to speed up the network. The proposed method is compared with the traditional network, and the result shows the proposed method improves the performance of the network. The learning speed is improved by 35% using 100 neurons within a layer. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Power Quality Evaluation and Optimization of Sensor-less Field Oriented Controller on 32-bit ARM Cortex Microcontroller 基于32位ARM Cortex微处理器的无传感器场定向控制器的电能质量评估与优化
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885302
Xin Xue, Y. Teh
{"title":"Power Quality Evaluation and Optimization of Sensor-less Field Oriented Controller on 32-bit ARM Cortex Microcontroller","authors":"Xin Xue, Y. Teh","doi":"10.1109/MWSCAS.2019.8885302","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885302","url":null,"abstract":"Electronic speed controller (ESC) is an important subsystem in drones, which are used to control and regulate the speed of its electric motor. For the high-end drones which require longer flight times, higher dynamic behavior with smooth and stable performance, Field Oriented Controllers (FOC) which power three-phase sinusoidal back-EMF motors are typically used to provide the required high efficiency, small torque ripple and dynamic performance. This paper proposes an analysis method based on discrete Fourier transform (DFT) over the measured motor current, in order to optimize the system parameters such as modulation period, CPU clock frequency and power supply voltage. As proof of concept, a FOC-based ESC implemented in a generic 32-bit microcontroller is studied. Findings show that the power quality and motor dynamic performance of a FOC ESC depends strongly on modulation period and relatively insensitive with respect to CPU voltage and frequency scaling.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126550229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis 标准逻辑单元合成组合电路中的脉冲展宽
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885259
Semiu A. Olowogemo, W. H. Robinson, Ahmed Yiwere, Ebenezer Tachie-Menson, D. Limbrick, B. Lin
{"title":"Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis","authors":"Semiu A. Olowogemo, W. H. Robinson, Ahmed Yiwere, Ebenezer Tachie-Menson, D. Limbrick, B. Lin","doi":"10.1109/MWSCAS.2019.8885259","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885259","url":null,"abstract":"Technology scaling improves the power, area, and speed of an electronic design, but the reliability of newer technologies is impacted by the presence of radiation-induced transients; these transients are more pronounced in newer technologies. In the presence of variations due to process corners (P), operating voltage (V), and temperature (T), a transient pulse with no serious threat, which would be masked electrically, traverses more gates towards a storage element due to pulse broadening. In this paper, the transient pulses that initially pose no significant threat are simulated with PVT variations in arithmetic circuits from the EPFL benchmark suite to investigate the effect of variations on vulnerable gates. The results show that the variation enhances the transient pulses with no serious threat and causes pulse broadening from the locations of vulnerable gates. A mitigation approach is applied on the vulnerable gates of the sine circuit, and the masking capability during worst-case analysis improves on average by 76.5% for process corner variation, 85.5% for operating voltage variation, and 84.4% for temperature variation.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131627957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parallel Bayesian Belief Network in Building Energy Conservation 并行贝叶斯信念网络在建筑节能中的应用
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884976
Golrokh Mirzaei, Nima Mansouri, M. Jamali
{"title":"Parallel Bayesian Belief Network in Building Energy Conservation","authors":"Golrokh Mirzaei, Nima Mansouri, M. Jamali","doi":"10.1109/MWSCAS.2019.8884976","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884976","url":null,"abstract":"It is important to control processes efficiently in commercial buildings for Energy conservation. The key element for saving energy is to obtain accurate information about the occupancy, and if there is no one in the building then services such as Heating, Ventilation, and Air-conditioning (HVAC), lighting, etc. can be turned off. Also, it is very critical that the building services respond in real-time, as it may affect the functionality of employees/equipment in the building. This paper presents a fast occupancy detection technique using parallel Bayesian Belief Network. This technique can be used as a fast, reliable, and automated occupancy detection technique in commercial buildings.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Current Mirroring Integration Based Visible Light Receiver for Intelligent Transport Systems 基于CMOS电流镜像集成的智能交通系统可见光接收器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884993
Moaaz Ahmed, A. Bermak
{"title":"A CMOS Current Mirroring Integration Based Visible Light Receiver for Intelligent Transport Systems","authors":"Moaaz Ahmed, A. Bermak","doi":"10.1109/MWSCAS.2019.8884993","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884993","url":null,"abstract":"Visible light communication (VLC) is gaining immense popularity for its inherent energy-efficient and freely available wide unlicensed spectrum in a range of applications that include indoor positioning, medical and navigational equipments and smart vehicular networks. In this paper, we present a current mirroring integration (CMI) based VLC receiver for intelligent transport systems. Polarization property of light is used to reject ambient light interference by sending and receiving differential data over adjacent channels. Each channel transmit and receive complimentary data through a set of linear polarizers. The receiver front-end is based on differential CMI topology which integrates the photocurrent over a pair of capacitors followed by a differential charge transfer amplifier (CTA) which performs amplification of differential optical signal and cancellation of background (DC) light up to 100μA. This is followed by a differential comparator with D-flip flop to make decision and latch the resultant data in digital format. Designed and simulated in 0.18μm CMOS process, the proposed VLC receiver front-end consumes 42μA current and achieve data rate of 5MHz with energy consumption of 15pJ/bit.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131718024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Operating Temperature Based Vulnerabilities in ReRAM ReRAM中基于操作温度的漏洞
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885182
T. Schultz, R. Jha
{"title":"Operating Temperature Based Vulnerabilities in ReRAM","authors":"T. Schultz, R. Jha","doi":"10.1109/MWSCAS.2019.8885182","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885182","url":null,"abstract":"Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable non-volatile memory (NVM) technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<±1 V) at fast time-scales (~ 10-100 ns) that make them an attractive option for on-chip embedded memory applications or off-chip high density memory storage. Memory storage read/write schemes rely on specific timing, voltage, and sensing thresholds to change and determine the states of the devices. While several in-memory computing architectures with ReRAM have been proposed, the impact of chip operating temperatures on write and read operations of ReRAM and the impact on resistive states is not well studied. This paper reports the impact of the temperature on the ReRAM devices during the write and read operations.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123364321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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