A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking

Abstract

This paper proposes a pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency detector (BBFD) with applications in frequency-locking of 10 Gbps (giga-bits-persecond) serial links. Bang-bang frequency detection is performed using a pair of BDGDLs that digitize the logic-1 pulse of receiver oscillator and a reference clock. A redundant successive approximation register (SAR) driven by the output of the BBFD is used to generate the frequency control word (FCW) of the digitally controlled oscillator (DCO) of the receiver. A frequency detection decision can be made in only 4 cycles of the reference clock. The frequency error of the ADFLL utilizing the proposed BBFD is analyzed. The ADFLL is designed in a TSMC 65 nm 1.2 V CMOS and tested with a 5 GHz reference clock. Simulation results show the ADFLL achieves frequency lock in less than 10 ns with the maximum frequency error in the lock state is within the frequency error boundaries of the BBFD.