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2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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A Comparison of Artificial Neural Network(ANN) and Support Vector Machine(SVM) Classifiers for Neural Seizure Detection 人工神经网络(ANN)与支持向量机(SVM)分类器在神经癫痫检测中的比较
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-10-31 DOI: 10.1109/MWSCAS.2019.8884989
Mohamed A. Elgammal, H. Mostafa, K. Salama, A. Mohieldin
{"title":"A Comparison of Artificial Neural Network(ANN) and Support Vector Machine(SVM) Classifiers for Neural Seizure Detection","authors":"Mohamed A. Elgammal, H. Mostafa, K. Salama, A. Mohieldin","doi":"10.1109/MWSCAS.2019.8884989","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884989","url":null,"abstract":"In this paper, two different classifiers are software and hardware implemented for neural seizure detection. The two techniques are support vector machine(SVM) and artificial neural networks(ANN). The two techniques are pretrained on software and only the classifiers are hardware implemented and tested. A comparison of the two techniques is performed on the levels of performance, energy consumption and area. The SVM is pretrained using gradient ascent (GA) algorithm, while the neural network is implemented with single hidden layer. It is found that the ANN consumes more power than the SVM by a factor of 4 with almost the same performance. However, the ANN finishes classification in much less number of clock cycles than the SVM by a factor of 34.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127444847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Bidirectional Interleaved Buck/Boost DC-DC Converter Design to Improve Power Density in High-Current Applications 在大电流应用中提高功率密度的双向交错降压/升压DC-DC变换器设计
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885244
Joseph Edler, N. Kondrath
{"title":"Bidirectional Interleaved Buck/Boost DC-DC Converter Design to Improve Power Density in High-Current Applications","authors":"Joseph Edler, N. Kondrath","doi":"10.1109/MWSCAS.2019.8885244","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885244","url":null,"abstract":"Interleaved topologies are popular in high-power, high-current applications due to the reduction in device current stresses and filter sizes. Despite its popularity, a proper design procedure for bidirectional interleaved dc-dc converter operating in CCM including the selection of appropriate number of phases and passive component design to optimize converter efficiency is missing in the literature. This paper presents a comprehensive design procedure for a bidirectional interleaved buck/boost dc-dc converters for high-current applications. Use of silicon carbide devices in the converter will further improve its efficiency and power density.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115662157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Near-Linear-Phase IIR Filters Using Gauss-Newton Optimization 基于高斯-牛顿优化的近线性相位IIR滤波器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885116
Jasper Tan, C. Burrus
{"title":"Near-Linear-Phase IIR Filters Using Gauss-Newton Optimization","authors":"Jasper Tan, C. Burrus","doi":"10.1109/MWSCAS.2019.8885116","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885116","url":null,"abstract":"In this paper, we present a simple optimization-based method for designing near-linear-phase IIR filters based on the Gauss-Newton method, and we explore its benefits over symmetric FIR filters. We demonstrate IIR low-pass filters with lower group delay, lower order, and lower magnitude errors than corresponding FIR filters while still maintaining a phase response linearity of R2 ≥ 0.99 in the passband. Such filters can be beneficial in applications where approximate, rather than exact, linear phase is sufficient. Code is available on the author’s website.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121134773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.6 MHz Bandwidth, 3rd/5th Order Active-RC Polyphase Filter with Quadrature Offset Cancellation for Low-IF GPS Radio 用于低中频GPS无线电的2.6 MHz带宽、3 /5阶正交偏移抵消有源rc多相滤波器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885262
S. Delshadpour
{"title":"A 2.6 MHz Bandwidth, 3rd/5th Order Active-RC Polyphase Filter with Quadrature Offset Cancellation for Low-IF GPS Radio","authors":"S. Delshadpour","doi":"10.1109/MWSCAS.2019.8885262","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885262","url":null,"abstract":"In this paper a low power active-RC filter exhibiting a reconfigurable transfer function, 3rd/5th order Butterworth, integrated in a low IF GPS receiver and fabricated in 0.35um SiGe BiCMOS technology is presented. This 17/26 dB gain filter has a bandwidth of 2.6MHz which is centered at 4.1MHz. It drains 1/1.25mA from a 2.7V supply in 3rd/5th order modes. The average in-band image rejection of this 0.58 mm2 filter is better than 25dB. This trimmed filter employs a quadrature offset cancellation circuit to remove all the available offset coming from the mixer output and its own mismatches.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125003695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Welcome to MWSCAS 2019 欢迎来到MWSCAS 2019
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/mwscas.2019.8885378
{"title":"Welcome to MWSCAS 2019","authors":"","doi":"10.1109/mwscas.2019.8885378","DOIUrl":"https://doi.org/10.1109/mwscas.2019.8885378","url":null,"abstract":"","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Signal Source Chip at 140GHz and 160GHz for Radar Applications in a SiGe Bipolar Technology 一种用于SiGe双极技术雷达应用的140GHz和160GHz信号源芯片
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885171
Matthias Völkel, Mohamed Thouabtia, Sascha Breun, K. Aufinger, R. Weigel, A. Hagelauer
{"title":"A Signal Source Chip at 140GHz and 160GHz for Radar Applications in a SiGe Bipolar Technology","authors":"Matthias Völkel, Mohamed Thouabtia, Sascha Breun, K. Aufinger, R. Weigel, A. Hagelauer","doi":"10.1109/MWSCAS.2019.8885171","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885171","url":null,"abstract":"In this paper, a monolithic signal source chip at 140GHz and 160 GHz including two VCOs, a dynamic divider and a static divider chain is presented. Two signal sources with these high fundamental frequencies are realized. All components have been designed using a 0.13µm 250GHz fT SiGe BiCMOS technology. The whole integrated circuit has a size of 930µm x 600µm including bondpads and consumes 210mA from a 3.3V and 130mA from a 1.8V supply. The oscillators cover a frequency range from 119.3–147.7GHz and 154.2–164GHz, which results in a tuning range of 28.4GHz and 9.8GHz. A output power of −0.9/3.6dBm with a best case phase noise of −111.2/−108dBc/Hz at 1MHz offset, measured at the divider output for PLL stabilization is achieved.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115323762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration 时间模式全数字Delta-Sigma时间-数字转换器与过程不确定度校准
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885152
F. Yuan, Parth Parekh
{"title":"Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration","authors":"F. Yuan, Parth Parekh","doi":"10.1109/MWSCAS.2019.8885152","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885152","url":null,"abstract":"This paper studies the impact of process uncertainty on a time-based all-digital ∆Σ time-to-digital converter (TDC) with a differential pre-skewed bi-directional gated delay line (BDGDL) time integrator. The principle and design of the TDC are presented first. It is followed with an in-depth investigation of the impact of process uncertainty on the building blocks of the TDC. An effective calibration technique capable of minimizing the impact of process uncertainty on the performance of the TSC is proposed. The TDC is designed in a 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. Simulation results demonstrate that process spread has a significant impact of the delay of the building blocks of the TDC subsequently the performance of the TDC. The detrimental impact of process uncertainty can be minimized by optimizing the TDC at SS (slow NMOS/slow PMOS) corner and adjusting the delay of the key delay blocks and that of the gated delay stages of the TDC in TT (typical NMOS/typical PMOS) and at FF (fast NMOS/fast PMOS) corner to their respective SS-corner value.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116407842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Supervising Communication SoC for Secure Operation Using Machine Learning 使用机器学习监督通信SoC的安全操作
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885273
Abdelrahman Elkanishy, Abdel-Hameed A. Badawy, P. Furth, L. Boucheron, Christopher P. Michael
{"title":"Supervising Communication SoC for Secure Operation Using Machine Learning","authors":"Abdelrahman Elkanishy, Abdel-Hameed A. Badawy, P. Furth, L. Boucheron, Christopher P. Michael","doi":"10.1109/MWSCAS.2019.8885273","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885273","url":null,"abstract":"Manufacturers normally buy and/or fabricate communication chips using third-party suppliers, which are then integrated into a complex hardware-software stack with a variety of potential vulnerabilities. This work proposes a compact supervisory circuit to classify the operation of a Bluetooth (BT) SoC at low frequencies by monitoring the input power and radio frequency (RF) output of the BT chip passed through an envelope detector. The idea is to inexpensively fabricate an envelope detector, power supply current monitor, and classification algorithm on a custom low-frequency integrated circuit in a trusted legacy technology. When the supervisory circuit detects unexpected behavior, it can shut off power to the BT SoC. In this preliminary work, we proto-type the supervisory circuit using off-the-shelf components. We extract simple yet descriptive features from the envelope of the RF output signal. Then, we train machine learning (ML) models to classify different BT operation modes, such as BT advertising and transmit modes. Our results show ∼100% classification accuracy.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A numerical methodology for a 6 DOF pose estimation with 3D magnetic field sensors 基于三维磁场传感器的六自由度姿态估计的数值方法
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885265
Phil Meier, K. Rohrmann, Marvin Sandner, M. Prochaska
{"title":"A numerical methodology for a 6 DOF pose estimation with 3D magnetic field sensors","authors":"Phil Meier, K. Rohrmann, Marvin Sandner, M. Prochaska","doi":"10.1109/MWSCAS.2019.8885265","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885265","url":null,"abstract":"Linear and angular position sensing using magnetic field sensors play a decisive role in automotive, industrial and consumer applications. Recently powerful 3D Hall sensors have become available, which enable simple measurement setups for 3D position sensing. In this paper a numerical concept for the determination of linear and angular position in the three-dimensional space is presented, which bases on an analytic model of an encoder magnet. To prevent numerical instabilities, a modified Newton-Raphson algorithm with adaptive dynamic step size control is used. Simulation results validate the applicability of our approach.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122941481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
HLS Based Optimizations of an FPGA Hardware Design for Plenoptic Image Processing Algorithm 基于HLS的FPGA全光图像处理算法硬件设计优化
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885282
Faraz Bhatti, Thomas Greiner
{"title":"HLS Based Optimizations of an FPGA Hardware Design for Plenoptic Image Processing Algorithm","authors":"Faraz Bhatti, Thomas Greiner","doi":"10.1109/MWSCAS.2019.8885282","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885282","url":null,"abstract":"Optical 3D image processing algorithms are used in a wide range of applications, such as research, healthcare, industry automation. Generally, such algorithms consist of computation intensive instructions. The performance of general purpose processor based system is a bottleneck because of its sequential nature. FPGA based hardware solution can be an alternative for such problems. Due to its architecture, FPGA can exploit spatial and temporal parallelization and hence the performance with respect to execution time and area can be improved. However, creating hardware with the help of a hardware description language (HDL), such as VHDL, is a complex and time taking process. High-level synthesis (HLS) tools can be employed to resolve this issue. This paper discusses the approach to optimize the HLS based hardware architecture for plenoptic 3D image processing algorithm. It is an iterative process that requires low-level knowledge of the hardware workflow. The results show that the performance is improved.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122849056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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