HLS Based Optimizations of an FPGA Hardware Design for Plenoptic Image Processing Algorithm

Optical 3D image processing algorithms are used in a wide range of applications, such as research, healthcare, industry automation. Generally, such algorithms consist of computation intensive instructions. The performance of general purpose processor based system is a bottleneck because of its sequential nature. FPGA based hardware solution can be an alternative for such problems. Due to its architecture, FPGA can exploit spatial and temporal parallelization and hence the performance with respect to execution time and area can be improved. However, creating hardware with the help of a hardware description language (HDL), such as VHDL, is a complex and time taking process. High-level synthesis (HLS) tools can be employed to resolve this issue. This paper discusses the approach to optimize the HLS based hardware architecture for plenoptic 3D image processing algorithm. It is an iterative process that requires low-level knowledge of the hardware workflow. The results show that the performance is improved.