{"title":"Process Specific Functions for Assurance of Analog/Mixed-Signal Integrated Circuits","authors":"M. Casto, B. Dupaix, P. Orlando, W. Khalil","doi":"10.1109/MWSCAS.2019.8884938","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884938","url":null,"abstract":"This paper investigates the process-induced variation response of analog and mixed-signal ICs to yield anti-counterfeiting and anti-cloning design techniques. It defines unique behaviors called Process Specific Functions (PSFs) that identify circuits of the same pedigree and provide traits for authentication and individual chip identification. To demonstrate PSF utility, expansion of quantization sampling theory is used to produce a statistically bounded digital to analog converter uniqueness model. A parameter space of normalized, challenge driven, non-linear harmonic amplitude responses are then correlated to random and systematic process variations to produce distributions for probability of detection and probability of false alarm statistics. These authenticity characteristics are related to process models to provide a novel analog IC supply chain risk management technology.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128638862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Synchronization and secure transmission of data in incommensurate fractional-order chaotic systems using a sigmoid-like controller","authors":"J. Mata-Machuca, R. Aguilar-López","doi":"10.1109/MWSCAS.2019.8884982","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884982","url":null,"abstract":"In this contribution a control scheme for a class of fractional-order chaotic systems and its application in the synchronization and secure transmission of data problems is designed. The asymptotic stability of the synchronization error and the ultimate bound of the information recovery error are established employing the fractional Lyapunov direct method. The proposed sigmoid-like controller is used as input to the receiver system whose states are asymptotically synchronized with the transmitter system. The technique has been applied in the synchronization and secure communications of the incommensurate fractional-order Rössler and Chen systems.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128642619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data Augmentation for Face Recognition System Implemented in Multiple Transform Domains","authors":"Ramy C. G. Chehata, W. Mikhael","doi":"10.1109/MWSCAS.2019.8885339","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885339","url":null,"abstract":"A face recognition system which represents each of the augmented facial images as a superposition of the dominant components in two transform domains is proposed. Each face in the spatial domain is divided into horizontal, vertical halves and diagonal format. These partitions are concatenated to generate four more faces per subject in any database used. All images are first preprocessed then compressed using two different domains. The Discrete Wavelet Transform (DWT) and the Discrete Cosine Transform (DCT). Accordingly, each face will have two feature matrices. A voting scheme is used to define ground truth identity. The performance of the proposed system is evaluated using k-fold cross validation of ORL, Yale and FERET databases. Sample results are presented. The proposed technique achieves higher recognition rates while retaining 74% savings in storage recently reported.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gain Kim, Woohyun Kwon, T. Toifl, Y. Leblebici, Hyeon-Min Bae
{"title":"Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link","authors":"Gain Kim, Woohyun Kwon, T. Toifl, Y. Leblebici, Hyeon-Min Bae","doi":"10.1109/MWSCAS.2019.8885299","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885299","url":null,"abstract":"For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from the extreme process node shrinkage. This paper discusses the design of >56Gb/s DAC/ADC-based wireline transceiver (TRX) with discrete multi-tone (DMT) modulation. Some notable differences between wireless orthogonal frequency division multiplexing (OFDM) systems and wireline DMT systems are discussed, and some practical design considerations for a multiple tens-of-Gb/s DMT RX is provided.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130569183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-decompressing FPGA Bitstreams","authors":"Shenghou Ma, P. Ampadu","doi":"10.1109/MWSCAS.2019.8885346","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885346","url":null,"abstract":"SRAM based FPGAs (field programmable gate arrays) are volatile devices, and need to reload its configuration (bitstream) every time after power up. Bitstream compression is one of the major method to reduce the cost of storing the configuration storage and speed up configuration. However, existing complete bitstream (as compared to partial bitstream) compression methods require an external decompresser implemented either in another FPGA or CPU. This drawback prevents deployment of bitstream compression to already in-field systems. This paper drew inspiration from self-extracting archive, and utilizes the self partial reconfiguration capabilities of modern FPGAs to create a self-decompressing FPGA bitstreams so that the decompression engine is located inside the compressed bitstream itself. Analysis showed that this method will never increase the size of bitstream, and can achieve configuration time reduction whenever the compression ratio is smaller than 7/9 and the configuration reduction scales almost linearly with the compression ratio. Furthermore, the paper shows that by using bitstream assembly techniques, it is possible to choose the compression algorithm after building the target bitstream, therefore, the best compression ratio can be achieved given a pool of available decompression engines.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121063687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Tunable Bandstop Filter Based on Source Follower","authors":"F. T. Almutairi, A. Karsilayan","doi":"10.1109/MWSCAS.2019.8885030","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885030","url":null,"abstract":"A tunable bandstop filter based on source follower is presented. The filter is designed using a source follower architecture with partial positive feedback and feed-forward paths using 0.18µm CMOS technology. The filter consumes about 1.4 mW from a 1.8V power supply, and it is designed to have 1.5GHz center frequency with 360 MHz bandwidth and 80 dB attenuation. The filter achieves 10 dBm IIP3 for two tones at 1.495GHz and 1.505 GHz.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121664254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmed Aldhahab, Taif Alobaidi, A. Q. Althahab, W. Mikhael
{"title":"Applying Multiresolution Analysis to Vector Quantization Features for Face Recognition","authors":"Ahmed Aldhahab, Taif Alobaidi, A. Q. Althahab, W. Mikhael","doi":"10.1109/MWSCAS.2019.8885188","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885188","url":null,"abstract":"In this paper, an approach of Facial Parts Detection (FPD) followed by the Discrete Wavelet Transform (DWT) in conjunction with Vector Quantization (VQ) algorithm for Facial Recognition (FR) are proposed. The FR system contains two modes: Training, and Classification. The proposed FR modes contain Preprocessing step followed by the Feature Extraction. The Classification mode yields the identification. The FPD detects nose, both eyes, and mouth for each pose in the Preprocessing step. Then, DWT is employed for each part that is detected for feature selection and data reduction. Thereafter, for further compaction and discrimination, the VQ, with the Kekre Fast Codebook Generation (KFCG) initialization method, is employed to form the final model that contains four feature groups per person. The DWT and VQ are utilized to reduce final feature dimensions without affecting discrimination. The recognition accuracy is calculated using the Euclidean distance. The four databases that are utilized to test the performance of the proposed FR system are: Georgia Tech, YALE, FEI, and FERET. The poses in these databases have various illumination conditions, face rotation, facial expressions, etc. The results, from which samples are presented here, of the FR system and other techniques are obtained and then examined using the Cross Validation based on K-fold method. The proposed FR is shown to improve the recognition accuracies while significantly reducing the storage requirements with comparable computational complexity.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127790107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Security Taxonomy in IoT – A Survey","authors":"Phillip Williams, P. Rojas, M. Bayoumi","doi":"10.1109/MWSCAS.2019.8884913","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884913","url":null,"abstract":"Internet of Things (IoT) devices have been identified as the primary source or compromised node responsible for the recent increase in reported cases of network intrusion attacks. Research on the vulnerabilities of IoT devices, reveals in most cases the root cause of the vulnerabilities is the incorrect implementation of security features or the absence of security features. The number of network intrusion will increase as new IoT technologies with lacking security features are implemented in many sectors of society such as, transportation, business, industry, and home. There are three goals of this survey. First, classify security features in IoT devices. Second, provide answers to two main questions that researchers, system administrators, and the general public need to know before installing IoT devices in their network: what are the security features offered by the device? and what are the security threats faced by the device? With answers to these questions, we will be able to make well-informed decisions when integrating such devices in our network. Third, highlight the importance of integrating security features in the development and design of IoT devices, rather than treating it as an afterthought.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Curvature Compensated Bandgap Circuit Exploiting Temperature Dependence of β","authors":"Radha Krishna Mothukuru, Manish Kumar, B. Sahoo","doi":"10.1109/MWSCAS.2019.8885233","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885233","url":null,"abstract":"This paper proposes a technique for the curvature compensation in Bandgap references to obtain a better Temperature Coefficient (TC). The proposed method is based on the fact that the Bipolar junction transistors used in Bandgap references have finite Beta which is temperature dependent. As β of NPN transistors in CMOS process is very low, Darlington configuration is used to achieve larger β to achieve the desired curvature compensation. Designed and simulated in TSMC 180-nm CMOS process the proposed bandgap circuit achieves a temperature coefficient of 9.9 ppm/°C across a temperature range of −40°C to 125°C and a line regulation from 1.6 V to 4.0 V.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134009026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC","authors":"Jiu Xiong, Jiajun Ren, Jin Liu","doi":"10.1109/MWSCAS.2019.8885195","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885195","url":null,"abstract":"This paper presents a 2b/cycle asynchronous SAR ADC with a capacitive divider based RC-DAC. The new architecture reduces the number of capacitors and resistors, leading to a smaller die area and lower hardware cost. It also allows for a new timing scheme with a merged samplingconversion cycle to increase the conversion speed. An 8-b SAR ADC with the proposed architecture is designed in 180nm CMOS technology operating at sampling rate of 65MS/s. The postlayout simulation shows the proposed SAR ADC can achieve SNDR of 45.16dB at near-Nyquist frequency and occupies an active area of 0.045mm2. The FOM under a 1.2V&1.8V supply voltage is 216fJ/conversion-step with power consumption of 2.07mW.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134414890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}