2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

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Power Optimization of Arduino-Based Sensor System for Salton Sea Environmental Monitoring 基于arduino的索尔顿海环境监测传感器系统的功耗优化
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8884880
Kristian Diaz, Y. Teh
{"title":"Power Optimization of Arduino-Based Sensor System for Salton Sea Environmental Monitoring","authors":"Kristian Diaz, Y. Teh","doi":"10.1109/MWSCAS.2019.8884880","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884880","url":null,"abstract":"Commercial-off-the-shelf (COTS) microcontroller based embedded system and sensors are used to monitor the Salton Sea environmental hazard. Power consumption data of microcontroller CPU core, I/O buses (UART, SPI and I2C), and peripheral sensors (GPS and optical-based dust sensor) are first presented, followed by optimization techniques using software control and hardware-assisted power gating technique. A set of logic based on sensor input is introduced to create a conscious way to optimize system power. Caveats of hidden power cost during field operation of peripheral sensors are also discussed. Our findings show that a conscious power-optimized design can simultaneously extend system run time to collect additional data up to 84% higher compared to LEAP-like approach.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114991694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Remote FPGA Lab For ZYNQ and Virtex-7 Kits 用于ZYNQ和Virtex-7套件的远程FPGA实验室
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885064
A. Mohsen, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, M. Asy, H. Mostafa
{"title":"Remote FPGA Lab For ZYNQ and Virtex-7 Kits","authors":"A. Mohsen, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, M. Asy, H. Mostafa","doi":"10.1109/MWSCAS.2019.8885064","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885064","url":null,"abstract":"This paper proposes a remotely programmable and interactive ZYNQ and Virtex-7 FPGA (Field Programmable Gate Array) Lab for testing and implementing arbitrary hardware circuit designs on real hardware. The online virtual lab facilitates the use of FPGA Boards in simple steps and provides graphical and command line interface to control and monitor FPGA signals in real time. The remote lab provides a scheduling system and allows multiple concurrent remote users. The remote interaction method doesn’t depend on the type of the device; so it can be scaled to include different devices. The required hardware and software of the remote laboratory is developed, implemented and tested by the undergraduate and graduate students at Cairo University in Egypt.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On Sensitivity of Bias Operation Point In Transistors with Moderate Inversion 中等反转晶体管偏置工作点灵敏度的研究
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885047
I. Filanovsky, L. Oliveira
{"title":"On Sensitivity of Bias Operation Point In Transistors with Moderate Inversion","authors":"I. Filanovsky, L. Oliveira","doi":"10.1109/MWSCAS.2019.8885047","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885047","url":null,"abstract":"The paper analyses sensitivity, with respect to the threshold voltage, of bias operation point in the analog circuits using moderate inversion. It is shown that this regime is highly sensitive with respect to the threshold voltage variation. Such high sensitivity imposes unrealistic requirements on the threshold voltage tolerances, so that it is practically impossible to design an amplifier with moderate inversion in the stages without adaptable or tunable threshold voltage. It is also shown that, as a result of this mode of inversion, some important design metrics (cancelling of the third order distortion) are unrealizable.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 5.4 Gbps Protocol Based CMOS Limiting ReDriver for Type-C Applications 基于5.4 Gbps协议的c型CMOS限制重驱动
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885381
S. Delshadpour, C. Speelman
{"title":"A 5.4 Gbps Protocol Based CMOS Limiting ReDriver for Type-C Applications","authors":"S. Delshadpour, C. Speelman","doi":"10.1109/MWSCAS.2019.8885381","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885381","url":null,"abstract":"PCB traces have high-frequency losses due to skin effect and dielectric losses which result in inter symbol interference (ISI), as the signal passes through cable and PCB traces. A limiting ReDriver, which acts as a repeater and includes a continuous time equalizer, removes the ISI which results in a longer signal reach. A CMOS limiting ReDriver channel operating up to 5.4Gbps and programmable preemphasis and de-emphasis to be compliant with some of the standards like display port (DP) and USB, is presented. It has programmable peaking gain up to 12dB at 2.7GHz with 1.5dB steps to compensate for the channel loss and a programmable output swing control of 400mVpp up to 1100mVppd. It has been implemented in 0.14 um CMOS technology and consumes 37.5mA to 55.5mA per channel from a 1.8V supply, depending on selected output swing and emphasis level. It uses common mode keeper, far-end termination detector and incoming squelch detector to work inside a protocol based ReDriver chip.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133039231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Imbalanced High-Current Multi-Phase Buck Converters for High-Performance CPUs 用于高性能cpu的不平衡大电流多相降压转换器
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885141
Manmeet Singh, A. Fayed
{"title":"Imbalanced High-Current Multi-Phase Buck Converters for High-Performance CPUs","authors":"Manmeet Singh, A. Fayed","doi":"10.1109/MWSCAS.2019.8885141","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885141","url":null,"abstract":"High-performance CPUs require buck converters with high-current ratings (4-12 A), fast dynamic response, and high efficiency across a wide load range. The most common approach for realizing such buck converters is the conventional multi-phase topology with phase-shedding, where all the active phases are identical in terms of the inductor, the switching frequency, and the share of the total load current, i.e. balanced phases. Instead, this paper proposes using a different inductor, switching frequency, and share of the total load current for each individual phase, i.e. imbalanced phases. This approach provides additional degrees of freedom by the independent choice of the inductor and the switching frequency of each phase, which enables higher maximum load current rating and higher efficiency across the entire load current range compared to conventional balanced multi-phase designs. To demonstrate the viability and the advantages of imbalanced multi-phase buck converters in high-current application, a 12-A 4-phase design in 0.13-µm CMOS for high-performance CPUs is presented and compared to three conventional balanced reference designs in the same process technology.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130598484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new and Reliable Decision Tree Based Small-Signal Behavioral Modeling of GaN HEMT 基于决策树的GaN HEMT小信号行为建模
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885334
A. Khusro, M. Hashmi, A. Q. Ansari, Medet Auyenur
{"title":"A new and Reliable Decision Tree Based Small-Signal Behavioral Modeling of GaN HEMT","authors":"A. Khusro, M. Hashmi, A. Q. Ansari, Medet Auyenur","doi":"10.1109/MWSCAS.2019.8885334","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885334","url":null,"abstract":"The paper, for the first time, explores multivariable small signal modeling technique of GaN HEMT based on Decision tree. The proposed model presents a novel binary decision tree to model the GaN HEMT device for multi-biasing and broad frequency range. Bayesian algorithm has been used to find the optimal hyperparameters for better generalization capability and higher accuracy. An excellent agreement is found between the measured S-parameters and the proposed model for complete frequency range of 1GHz-18GHz.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Memristor-Based AES Key Generation for Low Power IoT Hardware Security Modules 基于忆阻器的低功耗物联网硬件安全模块AES密钥生成
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885031
Hanan Rady, H. Hossam, M.Sameh Saied, H. Mostafa
{"title":"Memristor-Based AES Key Generation for Low Power IoT Hardware Security Modules","authors":"Hanan Rady, H. Hossam, M.Sameh Saied, H. Mostafa","doi":"10.1109/MWSCAS.2019.8885031","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885031","url":null,"abstract":"Security of Internet of Things (IoT) needs devices and algorithms that offer ultra-low power consumption and a long lifespan, alongside strong immunity against attacks, lower chip area, and acceptable throughput. Hardware security using nanoelectronic technologies shows promise for the area and energy-efficient implementations in IoT. Owing to the recent advances in Memristor as a potential building block for future hardware, it becomes a vital issue to study the role that Memristor will play in hardware security. This work presents a hardware security module for low power IoT security implementations. The proposed module depends on Memristor-based AES key generation relying mainly on the uniqueness of Memristor devices due to fabrication process variations. In addition to taking into consideration the strength properties and great features of Time-based ADC and AES cryptographic algorithm, the proposed hardware security module could meet the needs of modern technology such as secure communication between IoT embedded devices.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125848358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of A 52.5 dB Neural Amplifier with Noise-Power Trade-off 噪声功率权衡的52.5 dB神经放大器设计
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885224
N. Tasneem, I. Mahbub
{"title":"Design of A 52.5 dB Neural Amplifier with Noise-Power Trade-off","authors":"N. Tasneem, I. Mahbub","doi":"10.1109/MWSCAS.2019.8885224","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885224","url":null,"abstract":"An accelerating interest in neuromodulation and brain-machine interfacing has resulted in the development of multi-channel neural signal recording systems over the past few decades. A critical part of the acquisition system is the analog front-end, which includes the neural amplifier with low-power and low-noise configuration in the sub-Hz operating frequency. This paper presents a neural signal recording amplifier that is capable of amplifying signals in the sub-Hz to kHz frequency range. The amplifier is designed in standard 0.5 µm CMOS process with a fully-differential architecture. The proposed operational transconductance amplifier (OTA) uses two-stage topology and a capacitive-resistive feedback technique to have the lower and the higher cut-off frequency as 0.125 Hz and 1.258 kHz respectively to record the low-frequency neural signals. It achieves a common-mode rejection ratio (CMRR) of 97.1 dB, a power supply rejection ratio (PSRR) of 84.4 dB. The amplifier achieves a mid-band gain of 52.53 dB with the total power consumption of 4.12 µW with a supply voltage of 3.3 V by making the transistors operate in the sub-threshold region. The amplifier is designed taking into account the noise-power trade-off, and the input-referred noise of the amplifier is found to be 3.16 µVrms over a bandwidth of 0.1 Hz- 5 kHz. The prototype single channel amplifier has an active die area of 0.28 mm2. The overall performance metrics of gain, power consumption and the noise performance of the proposed amplifier make it a good choice for neural signal recording applications.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123447571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Empirical Analysis of Fixed Point Precision Quantization of CNNs cnn定点精度量化的实证分析
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885263
Anaam Ansari, T. Ogunfunmi
{"title":"Empirical Analysis of Fixed Point Precision Quantization of CNNs","authors":"Anaam Ansari, T. Ogunfunmi","doi":"10.1109/MWSCAS.2019.8885263","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885263","url":null,"abstract":"Image classification, speech processing, autonomous driving, and medical diagnosis have made Convolutional Neural Networks (CNN) mainstream. Due to their success, many deep networks have been developed such as AlexNet, VGGNet, GoogleNet, ResidualNet [1]–[4],etc. Implementing these deep and complex networks in hardware is a challenge. There have been many hardware and algorithmic solutions to improve the throughput, latency and accuracy. Compression and optimization techniques help reduce the size of the model while maintaining the accuracy. Traditionally, quantization of weights and inputs are used to reduce the memory transfer and power consumption. Quantizing the outputs of layers can be a challenge since the output of each layer changes with the input. In this paper, we use quantization on the output of each layer for AlexNet and VGGNET16 sequentially to analyze the effect it has on accuracy. We use Signal to Quantization Noise Ratio (SQNR) to empirically determine the integer length (IL) as well as the fractional length (FL) for the fixed point precision. Based on our observations, we can report that accuracy is sensitive to fractional length as well as integer length. For AlexNet we observe deterioration in accuracy as the word length decreases. The results are similar in the case of VGGNET16.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"27 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123492868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Highly Efficient Broadband mm-Wave 24-32.5 GHz SiGe PA for Potential 5G Applications 面向潜在5G应用的高效宽带毫米波24-32.5 GHz SiGe PA
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI: 10.1109/MWSCAS.2019.8885209
J. Tsay, J. Mayeda, Jerry Lopez, D. Lie
{"title":"A Highly Efficient Broadband mm-Wave 24-32.5 GHz SiGe PA for Potential 5G Applications","authors":"J. Tsay, J. Mayeda, Jerry Lopez, D. Lie","doi":"10.1109/MWSCAS.2019.8885209","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885209","url":null,"abstract":"We present in this work a highly efficient broadband millimeter-wave power amplifier (mm-wave PA) design in a 90nm SiGe technology for potential 5G applications. The post-layout extraction simulations suggest that the PA achieves broadband power-added efficiency (PAE) >31.4%, gain >8.5 dB, and POUT,sat >13.3 dBm across 24-32.5 GHz, with peak PAE of 40.2% at 26 GHz. The PA shows good linearity with 16-QAM LTE 250 MHz modulated signal input, obtaining ACLR1 of -38.6/-37.3 dBc at 26 GHz with POUT,avg of 6.4 dBm. The PA is also robust against variation in bias VB = 0.83-0.85 V and supply VCC = 1.0-1.4 V and can be applicable toward multi-band 5G applications.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121797126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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