2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献

{"title":"Wave Digital Emulation of a Memristive Circuit to Find the Minimum Spanning Tree","authors":"K. Ochs, Dennis Michaelis, Enver Solan","doi":"10.1109/MWSCAS.2019.8884878","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884878","url":null,"abstract":"Self-organizing circuits are subject to current research because they are known to solve computationally complex tasks fast, energy efficient and can be implemented in integrated circuits with minimum space requirements. This is especially desired in contexts where the problem involves many components, such as neural networks, and the solution demands exhaustive computational effort. Networks which are centered around memristors have shown to be good candidates for such self-organizing, circuit-inspired solutions. One of many interesting problems include finding the minimum spanning tree in a graph, as it has applications in human learning in the context of the self-organizing discovery of information transport and hence topology formation. This work presents a memristive circuit to solve the minimum spanning tree in a directed, weighted graph of arbitrary size. Since the manufacturing process of memristors is generally complicated and costly, a software emulator based on wave digital principles is derived which provides a powerful tool for investigations with different memristor models to aid development processes.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Segmented Digital SiPM","authors":"V. Vinayaka, Sachin P. Namboodiri, Angsuman Roy, R. J. Baker","doi":"10.1109/MWSCAS.2019.8884970","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884970","url":null,"abstract":"A digital silicon photomultiplier (SiPM) using segmentation technique is designed, simulated and fabricated in the AMS 0.35 µm SiGe BiCMOS process. The digital SiPM is intended for photon counting applications. The digital SiPM consists of 16 avalanche photodiodes (APD) each with active area of 24 µm x 24 µm arranged in a 4x4 array with series 236 kΩ quench resistors. The SiPM has a peak responsivity at 490 nm wavelength and a fill factor of 12.6 %. The digital SiPM generates an output 5-bit digital word that indicates the number of APDs triggered in the SiPM array at the rising edge of clock. Simulation results show that the digital SiPM can work at a maximum speed of 100 MS/s and uses 64.6 mW of power. The digital SiPM occupies an area of 0.38 mm2.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116489837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gain and Bandwidth Enhanced Class-AB OTAs","authors":"S. Pourashraf, J. Ramírez-Angulo, A. Roman-Loera, Manaswini Gangineni","doi":"10.1109/MWSCAS.2019.8885270","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885270","url":null,"abstract":"Efficient class-AB OTAs with enhanced gain bandwidth, open loop gain, output current, and slew rate are presented. They are based on a gm-boosting technique (at least factor of two) and also use dynamically biased cascode transistors to achieve high gain and output currents much larger than the bias current. Measurement results of 180 nm CMOS test chip prototypes validate the improvements.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"141 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130923916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Least Lossy Piezoelectric Energy-Harvesting Charger","authors":"Siyu Yang, G. Rincón-Mora","doi":"10.1109/MWSCAS.2019.8885007","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885007","url":null,"abstract":"Wireless microsensors can operate indefinitely when they use ambient kinetic energy in motion to replenish the battery. Of available technologies, a switched inductor can draw the most power from a piezoelectric transducer. Power consumption, however, limits how much of that power the battery receives. This paper theorizes and shows that drawing and delivering power with an inductor from the transducer into the battery directly reduces the energy the inductor carries. With less energy, inductor current and related ohmic losses are lower. This way, ohmic losses can be up to 74% lower. This is why the switched-inductor bridge is the least lossy piezoelectric charger in the state of the art.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134209594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Auto-Tuned Transition Scheme in Bias-Flip Rectifier for Piezoelectric Energy Harvesting","authors":"R. Chaudhari, A. Maity","doi":"10.1109/MWSCAS.2019.8885092","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885092","url":null,"abstract":"The self-sustainable, ultra-low powered devices and sensor nodes are becoming quite popular just because of the availability of the micro-power generators. One of such micro-power generator is a piezoelectric energy harvester which converts the ambient mechanical vibration energy into the electrical energy. The piezoelectric energy harvester is capable of extracting 100’s of µW of power available. The most widely used interfacing circuit for the piezoelectric energy harvester is a bias-flip rectifier. In the conventional bias-flip rectifier, there is an inherent trade-off between the power extraction and the size of the external inductor. Based on the system demand, the designers often face challenges to generate a precise transition time for a particular value of the inductor. In this paper, an auto-tuned transition scheme for the bias-flip rectifier is presented. It is capable of generating and adjusting the transition time suitably based on the value of the inductor chosen. The proposed auto-tuned transition scheme is designed in 180 nm CMOS technology with a quiescent power consumption of 14.6 µW.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130825807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling","authors":"Rajath Bindiganavile, A. Tajalli","doi":"10.1109/MWSCAS.2019.8884807","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884807","url":null,"abstract":"This article analyzes the potentials of different signaling methods to reach very high data communication speeds over copper channels. As the available bandwidth is limited in this type of channels, sensitivity to ISI (inter-symbol interference) turns out to be the key parameter influencing both data rate, and energy consumption. Performance of some of the main common signaling methods, all based on non-return to zero (NRZ), used in wire-line communications, are examined for implementing short-reach links. Moreover, it is shown that a proper combination of spatial and amplitude domain coding improves the signal quality (i.e., eye opening), enabling data transfer rates beyond 112 Gb/s.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AI, IoT hardware and Algorithmic Considerations for Hearing aid and Extreme Edge Applications","authors":"R. Brennan","doi":"10.1109/MWSCAS.2019.8884886","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884886","url":null,"abstract":"Artificial Intelligence (AI) has made many significant advances over recent years. Starting out as mainly university research endeavors, recent significant breakthroughs have pushed the practicality of AI to the forefront. It is making fast inroads to traditional industrial applications and it is clear that given sufficient computing resources, AI is applicable to almost anything.The breakthrough referenced is mostly the result of the diligent persistence of a number of AI researchers in combination with large increases in available computation power to reconsider much deeper neural networks than previously used which were consistently rejected because of their large complexity reasons. Deep Neural Nets have proven to be an adept framework and up to solving the difficult challenges proven previous machine learning approaches could not solve.Recently, driven by enhanced computational power and necessity, edge applications have arisen to the forefront. Generally, now that cloud computing is available, a choice may be made where to locate the recognition engine, local to the data source or on the cloud where considerable computing resources are available.Hearing aids, a product on the edge now connected via one or more wireless links and fully immersed in IoT are the subject and consideration of this paper. It is natural to consider whether, via these links, remote computation is possible and appropriate for hearing aid applications. Difficulties arise when remote computation is attempted simply because the local data to be inferenced must be transmitted. Summarizing, utilizing remote computing for local recognition creates, two immediate problems: 1) the transmission of possibly private data across an insecure channel, and 2) the channel may not exist in remote or adverse transmission environments. Two further difficulties emerge in an important subset of applications, including hearing aids and hearable products: 1) Delay from the transmission latency required to obtain Cloud computation – although fast and capable – once the information is obtained and 2) Transmission power.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114241002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder","authors":"Yuta Ideguchi, N. Kamiya, Masashi Tawada, N. Togawa","doi":"10.1109/MWSCAS.2019.8885174","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885174","url":null,"abstract":"This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1 SC decoders of length N2 and a single SC decoder of length N1. While the N1 decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1 of N, and we show that an appropriate choice of N1 yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115011657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Facial Recognition System Employing Transform Implementations of Sparse Representation Method","authors":"Taif Alobaidi, W. Mikhael","doi":"10.1109/MWSCAS.2019.8885123","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8885123","url":null,"abstract":"A new discriminative sparse representation approach for robust face recognition via l2 regularization (SRFR) was recently published. In this paper, a face recognition system implementation employing coefficients from two non-orthogonal transform domains, namely, Two-Dimensional Discrete Wavelet Transform (2D DWT) and 2D Discrete Cosine Transform (2D DCT), is presented. The use of these coefficients in this Mixed Wavelet Cosine Sparse Representation for Face Recognition (MWCSRFR) system as features shown to appreciably lower the computational complexity and the final storage size while maintaining the high recognition rate of the SRFR. Extensive simulations were carried out on five face databases, namely, ORL, YALE, FERET, Cropped AR, and Georgia Tech. The improved properties of the MWCSRFR are proved as shown in the given sample results.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114291208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Variable Record Table: A Run-time Solution for Mitigating Buffer Overflow Attack","authors":"Love Kumar Sah, S. A. Islam, S. Katkoori","doi":"10.1109/MWSCAS.2019.8884869","DOIUrl":"https://doi.org/10.1109/MWSCAS.2019.8884869","url":null,"abstract":"We present a novel approach to mitigate buffer overflow attack using Variable Record Table (VRT). Dedicated memory space is used to automatically record base and bound information of variables extracted during runtime. We instrument frame pointer and function(s) related registers to decode variable memory space in stack and heap. We have modified Simplescalar/PISA simulator to extract variables space of six (6) benchmark suites from MiBench. We have tested 290 small C programs (MIT corpus suite) having 22 different buffer overflow vulnerabilities in stack and heap. Experimental results show that our approach can detect buffer overflow attack with zero instruction overhead with the memory space requirement up to 13Kb to maintain VRT for a program with 324 variables.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"51 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116829645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}