Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration

Abstract

This paper studies the impact of process uncertainty on a time-based all-digital ∆Σ time-to-digital converter (TDC) with a differential pre-skewed bi-directional gated delay line (BDGDL) time integrator. The principle and design of the TDC are presented first. It is followed with an in-depth investigation of the impact of process uncertainty on the building blocks of the TDC. An effective calibration technique capable of minimizing the impact of process uncertainty on the performance of the TSC is proposed. The TDC is designed in a 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. Simulation results demonstrate that process spread has a significant impact of the delay of the building blocks of the TDC subsequently the performance of the TDC. The detrimental impact of process uncertainty can be minimized by optimizing the TDC at SS (slow NMOS/slow PMOS) corner and adjusting the delay of the key delay blocks and that of the gated delay stages of the TDC in TT (typical NMOS/typical PMOS) and at FF (fast NMOS/fast PMOS) corner to their respective SS-corner value.