Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis

Technology scaling improves the power, area, and speed of an electronic design, but the reliability of newer technologies is impacted by the presence of radiation-induced transients; these transients are more pronounced in newer technologies. In the presence of variations due to process corners (P), operating voltage (V), and temperature (T), a transient pulse with no serious threat, which would be masked electrically, traverses more gates towards a storage element due to pulse broadening. In this paper, the transient pulses that initially pose no significant threat are simulated with PVT variations in arithmetic circuits from the EPFL benchmark suite to investigate the effect of variations on vulnerable gates. The results show that the variation enhances the transient pulses with no serious threat and causes pulse broadening from the locations of vulnerable gates. A mitigation approach is applied on the vulnerable gates of the sine circuit, and the masking capability during worst-case analysis improves on average by 76.5% for process corner variation, 85.5% for operating voltage variation, and 84.4% for temperature variation.