A 0.045- to 2.5- GHz Frequency Synthesizer with TDC-based AFC and Phase Switching Multi-Modulus Divider

Ang Hu, Dongsheng Liu, Ke-feng Zhang, Lan-qi Liu, X. Zou
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引用次数: 10

Abstract

A 0.045- to 2.5- GHz wideband frequency synthesizer (FS) employing time-to-digital converter (TDC) based automatic frequency calibration (AFC) method and phase switching multi-modulus divider (MMD) for quantization noise suppression is presented in this paper. The counter-based AFC method takes several reference cycles to calculate the instantaneous voltage controlled oscillator (VCO) frequency, while the proposed TDC-based technique needs only 2 cycles. In order to suppress the quantization noise caused by the sigma-delta modulator (SDM) in the MMD, the loop division step is reduced from 2 to 0.5 by adopting the phase switching (PS) technique. The FS is designed and simulated using TSMC 180nm RF CMOS process. The simulation results of the AFC time are less than 1.4 μs when employing a 48 MHz reference signal and the quantization noise is suppressed by 12 dB compared to the conventional MMD structure.
一种0.045至2.5 GHz频率合成器,具有基于tdc的AFC和相位开关多模分频器
提出了一种采用基于时数转换器(TDC)的自动频率校准(AFC)方法和相开关多模分频器(MMD)进行量化噪声抑制的0.045 ~ 2.5 GHz宽带频率合成器(FS)。基于计数器的AFC方法需要几个参考周期来计算瞬时电压控制振荡器(VCO)频率,而基于tdc的方法只需要2个参考周期。为了抑制MMD中sigma-delta调制器(SDM)带来的量化噪声,采用相位开关(PS)技术将环分步从2步降低到0.5步。采用台积电180nm射频CMOS工艺设计并仿真了该系统。仿真结果表明,采用48 MHz参考信号时,AFC时间小于1.4 μs,量化噪声比传统MMD结构抑制了12 dB。
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