一种新的可重构神经网络硬件结构

Kasem Khalil, Omar Eldash, Bappaditya Dey, Ashok Kumar, M. Bayoumi
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引用次数: 10

摘要

神经网络在学习应用中已经被广泛使用。对于硬件设计者来说,在硬件上实现神经网络是一项复杂而具有挑战性的任务,因为需要考虑许多超参数和权衡。本文提出了一种可重构前馈神经网络,可用于不同的应用场合。该方法可以灵活地更改节点组织以适应应用程序。该网络分为两部分:一部分在每一层有一个固定节点,另一部分包含可重构节点。可重构节点具有从一层切换到另一层的能力,以加快网络的速度。将该方法与传统网络进行了比较,结果表明该方法提高了网络的性能。在一层中使用100个神经元,学习速度提高了35%。采用VHDL和Altera Arria10 GX FPGA实现了该方法的硬件实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Reconfigurable Hardware Architecture of Neural Network
Neural networks have been commonly used in learning applications. Implementing a neural network on hardware is a complex and challenging task for hardware designers as many hyperparameters and trade-offs need to be considered. This paper presents a reconfigurable feed-forward neural network which can be used for different applications. The proposed method has the flexibility to change the node organization to be suitable for an application. The network is divided into two parts: one part has a fixed node in each layer and the second part includes the reconfigurable nodes. The reconfigurable nodes have the ability to switch from one layer to another to speed up the network. The proposed method is compared with the traditional network, and the result shows the proposed method improves the performance of the network. The learning speed is improved by 35% using 100 neurons within a layer. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA.
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