A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic

A Physical Unclonable Function (PUF) is a one-to-one (1:1) or a one-to-many(1:M) functional mapping operation. Given an input, which is termed as a Challenge, a PUF function produces response(s), which is termed as Response. Therefore, any PUF can be mathematically defined with its unique CRP behavior. Silicon PUFs can be implemented mainly for hardware security and thus to guarantee IP-protection. On the other side of the discussion, we are standing at the beginning of the quantum computation era, where we may start replacing all classical digital logics with the reversible logic ones. In conventional circuits, during any digital logic operation, we generally loose bits of input information (fan-in) at the output end (fan-out) and which results in unavoidable dissipation of a significant amount of energy. In reversible logic operation, we can preserve any inputoutput information bits at the input as well as output end and thus this technology can be implemented to minimize significant heat dissipation and power consumption for a fully functional physical chip while increasing the speed. The only trade-off will be designing complexity and wafer area which is our future research focus. In this paper, we propose the reversible logic design for an existing XOR Gate based Low-Cost Congurable RO PUF structure based on Feynman gate as a reversible logic block. A comparative analysis between classical and quantum logic function is also given on various parameters along with limitations of conventional computing. The proposed approach is implemented using VHDL on Xilinx-7 FPGA.