开关电容功率变换器驱动中电荷复用分析

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI:10.1109/MWSCAS.2019.8884823

Mark Lipski, S. Gregori

{"title":"开关电容功率变换器驱动中电荷复用分析","authors":"Mark Lipski, S. Gregori","doi":"10.1109/MWSCAS.2019.8884823","DOIUrl":null,"url":null,"abstract":"This paper presents a method of reducing the power lost when driving the gate capacitance of CMOS transistors in switched-capacitor power converters. The consequences of the increased rise and fall times on the transistor on resistance are investigated. Additionally, the effectiveness of charge reuse on the transistors of a switched-capacitor voltage doubler is simulated in 65-nm CMOS technology resulting in efficiency improvements.","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analysis of Charge Reuse in Switched-Capacitor Power-Converter Drivers\",\"authors\":\"Mark Lipski, S. Gregori\",\"doi\":\"10.1109/MWSCAS.2019.8884823\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method of reducing the power lost when driving the gate capacitance of CMOS transistors in switched-capacitor power converters. The consequences of the increased rise and fall times on the transistor on resistance are investigated. Additionally, the effectiveness of charge reuse on the transistors of a switched-capacitor voltage doubler is simulated in 65-nm CMOS technology resulting in efficiency improvements.\",\"PeriodicalId\":287815,\"journal\":{\"name\":\"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2019.8884823\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2019.8884823","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了一种减小开关电容功率变换器中CMOS晶体管栅极电容驱动时功率损耗的方法。研究了上升和下降次数增加对晶体管电阻的影响。此外，在65纳米CMOS技术中，模拟了开关电容倍压器晶体管上电荷复用的有效性，从而提高了效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of Charge Reuse in Switched-Capacitor Power-Converter Drivers

This paper presents a method of reducing the power lost when driving the gate capacitance of CMOS transistors in switched-capacitor power converters. The consequences of the increased rise and fall times on the transistor on resistance are investigated. Additionally, the effectiveness of charge reuse on the transistors of a switched-capacitor voltage doubler is simulated in 65-nm CMOS technology resulting in efficiency improvements.

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来源期刊

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

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