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Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)最新文献

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Designing for signal integrity in high speed systems 高速系统信号完整性设计
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346794
L. Heid, M. Degerstrom, C. Nelson, E. Priest, G. Katopis
{"title":"Designing for signal integrity in high speed systems","authors":"L. Heid, M. Degerstrom, C. Nelson, E. Priest, G. Katopis","doi":"10.1109/ECTC.1993.346794","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346794","url":null,"abstract":"Designers of high speed digital systems are familiar with the concept of AC noise margin which encompasses simultaneous switching, reflections, and crosstalk. Designing for first incident switching and timing accuracy are common parameters. However, as system frequencies increase, these guidelines are not adequate to ensure fault free system operation. In addition to guaranteeing first incident switching and restricting the plateauing of the transition edges in the threshold region, \"area of vulnerability\" criteria has been identified. This criteria guarantees the integrity of the circuit's signal over the critical portion of its cycle time and evaluates the sharpness of the transition edges. Not only does this reduce the likelihood of false switching and intermittent noise problems, it increases the accuracy of the timing equations which is essential in high speed systems. This technique also has the flexibility to emphasize different criteria depending on the system requirements.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115177957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-chip piezoresistive stress measurement and 3D finite element simulations of plastic DIL 40 packages using different materials 采用不同材料的塑料DIL 40封装片上压阻应力测量和三维有限元模拟
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346844
H.C.J.M. van Gestel, L. van Gemert, E. Bagerman
{"title":"On-chip piezoresistive stress measurement and 3D finite element simulations of plastic DIL 40 packages using different materials","authors":"H.C.J.M. van Gestel, L. van Gemert, E. Bagerman","doi":"10.1109/ECTC.1993.346844","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346844","url":null,"abstract":"A full matrix of 8 different configurations of a plastic DIL 40 package has been measured. The materials used in the package consisted of a copper or an alloy 42 lead frame, a standard conductive die-attach adhesive or a special low stress type of die-attach adhesive and a standard moulding compound or a low stress compound. The stress measurements were performed with a test chip based on the piezoresistive effect. The numerical simulations ham been carried out to verify the results and to gain more insight in the deformations inside the package. Though the results are achieved for an dual in line package some results will also be valid for other types of plastic packages.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Fine pitch assembly techniques and processes using reflow soldering 使用回流焊的细间距组装技术和工艺
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346786
J.R. Ganasan, Y.F. Lee
{"title":"Fine pitch assembly techniques and processes using reflow soldering","authors":"J.R. Ganasan, Y.F. Lee","doi":"10.1109/ECTC.1993.346786","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346786","url":null,"abstract":"The requirements for Fine Pitch Technology (FPT) reflow soldering becoming ever increasing in surface mount assemblies. A good first pass yield can be realistically achieved through the proper implementation and control of reflow processes. In this context the authors discuss reflow options, assembly and defect evaluation.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127390612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A heuristic force-height equation for molten axisymmetric solder joints 熔融轴对称焊点的启发式力-高度方程
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346694
L.S. Goldman
{"title":"A heuristic force-height equation for molten axisymmetric solder joints","authors":"L.S. Goldman","doi":"10.1109/ECTC.1993.346694","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346694","url":null,"abstract":"A heuristic equation is developed which relates the height of a molten joint to its surface tension, geometric constraints, and the applied force. In its present state, the equation is valid only for heights varying up to 10% from the zero-load shape, although a method is suggested to extend this range. The equation agrees well with published data derived from an exact solution, and with the data from a small laboratory experiment. The equation is intended as a practical tool for packaging engineers and designers who do not have access to the software needed to obtain the exact solution.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Stress related offset voltage shift in a precision operational amplifier 精密运算放大器中与应力相关的偏置电压偏移
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346764
S. Gee, T. Doan, K. Gilbert
{"title":"Stress related offset voltage shift in a precision operational amplifier","authors":"S. Gee, T. Doan, K. Gilbert","doi":"10.1109/ECTC.1993.346764","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346764","url":null,"abstract":"In molded DIP packaging die attach stresses and stresses due to the contraction of the molding compound lead to a complex state of stress on the die surface where active device elements are located. This paper summarizes experimentation to reduce the effects of packaging stresses upon offset voltage shift in a precision operational amplifier. Variables examined include circuit location, low stress mold compounds, silicone gel coatings, side braze versus molded DIP assembly and post assembly trim.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122247602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
System 901: low K, copper MCM-C packaging 系统901:低K，铜MCM-C封装
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346746
P. Donohue, J. P. Page, E. Thiele, Y. Hu, M. Saltzberg, S. A. Gallo
{"title":"System 901: low K, copper MCM-C packaging","authors":"P. Donohue, J. P. Page, E. Thiele, Y. Hu, M. Saltzberg, S. A. Gallo","doi":"10.1109/ECTC.1993.346746","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346746","url":null,"abstract":"To meet the packaging needs of today's larger faster IC's DuPont Electronics has developed system 901. It is based on a crystallizable cordierite dielectric for low K, high strength, silicon matched TCE, combined with high conductivity copper metallization. Processing is easily carried out either with copper electrodes in a H/sub 2/O/N/sub 2/ atmosphere or with CuO electrodes in a burnout/reduction/sinter sequence. In both modes, circuits meet packaging performance requirements, especially distortion-free camber, without the need for constrained-sintering. The achievement of these properties has required an understanding of the origin of the forces affecting sintering, and the development of modifiers to control those forces.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130618209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Double sided flexible carrier with discretes and thermally enhanced FCA/COF 具有离散和热增强FCA/COF的双面柔性载流子
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346857
Cynthia S. Milkovich, Michael A. Gaynes, J. S. Perkins
{"title":"Double sided flexible carrier with discretes and thermally enhanced FCA/COF","authors":"Cynthia S. Milkovich, Michael A. Gaynes, J. S. Perkins","doi":"10.1109/ECTC.1993.346857","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346857","url":null,"abstract":"This paper describes an electronic assembly that uses SMT components, wire bonded chips as well as area array chips attached to a flexible carrier. The wire bond chip is reworkable until encapsulation. Heat spreaders are attached to flip chips and wire bond chips with thermally conductive adhesives. Volume constraints imposed by a system design can he satisfied by populating both sides of a flexible carrier with components. Potential cost savings and reliability gains are possible with this electronic assembly design. A single flexible carrier with chips can replace multiple printed circuit cards and two levels of interconnection.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Current carrying capacity of copper conductors in printed wiring boards 印刷线路板中铜导体的载流能力
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346704
T. Pan, R. Poulson, H. D. Blair
{"title":"Current carrying capacity of copper conductors in printed wiring boards","authors":"T. Pan, R. Poulson, H. D. Blair","doi":"10.1109/ECTC.1993.346704","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346704","url":null,"abstract":"The effect of thermal management of the copper conductors on PWBs (printed wiring boards) having different dimensions and arrangements is discussed. Design charts have been generated to include the parameters of conductor thickness from 1 to 3 oz, width from 5 to 20 mils, spacing at 8 mils, board thickness from 31 to 62 mils, input current, and temperature rise up to 50/spl deg/C. The analysis is based on finite element modeling with a heat transfer film coefficient obtained from infrared thermal imaging analysis of a test board. Of all the geometric parameters considered, conductor width and spacing are the primary parameters influencing thermal resistance. Conductor thickness is next, and board thickness proves to be the least sensitive parameter.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134370137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Flip-chip encapsulation on ceramic substrates 陶瓷基板上的倒装芯片封装
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346835
J. Clementi, J. McCreary, T. Niu, J. Palomaki, J. Varcoe, G. Hill
{"title":"Flip-chip encapsulation on ceramic substrates","authors":"J. Clementi, J. McCreary, T. Niu, J. Palomaki, J. Varcoe, G. Hill","doi":"10.1109/ECTC.1993.346835","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346835","url":null,"abstract":"Flip-chip encapsulation has been shown to provide at least a 5-10/spl times/ improvement in fatigue life of C4 (controlled collapse chip connection) solder joints. IBM has developed, qualified and implemented encapsulation in production for a wide array of selected C4 footprint chips attached to ceramic substrates. In addition to providing a very substantial improvement in reliability, this technology has enabled major extensions to the flip-chip on ceramic menu by relaxing chip footprint or size constraints, accommodating larger chips and allowing smaller C4's on finer pitches. Also, new package technologies have evolved that feature thin and lightweight surface mountable designs that conform to industry outlines. IBM evaluated several encapsulant formulations and tested over 2000 encapsulated chips and 200000 individual C4's during the development and qualification phases. Test data was collected for a variety of accelerated thermal cycling (ATC) conditions and was supported by extensive finite element modeling. Chip configurations included memory and logic footprints and ranged in size to 14.7 mm chip size and 10.2 mm DNP (distance from neutral point of chip footprint). In all cases, ATC data showed a dramatic improvement in C4 life on encapsulated chips with no adverse effects in other tests. Several different encapsulant formulations, each with minor variations, were evaluated, and the encapsulant dispense and cure process was optimized for ease of manufacturing high production volumes that are required by IBM.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Novel packaging technique for laser diode arrays using film carrier 基于薄膜载体的激光二极管阵列封装新技术
Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346755
M. Usui, K. Katsura, T. Hayashi, M. Hosoya, K. Sato, S. Sekine, H. Toba
{"title":"Novel packaging technique for laser diode arrays using film carrier","authors":"M. Usui, K. Katsura, T. Hayashi, M. Hosoya, K. Sato, S. Sekine, H. Toba","doi":"10.1109/ECTC.1993.346755","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346755","url":null,"abstract":"An innovative packaging technique for laser diode (LD) arrays has been developed. This technique uses a new film carrier which has high-density inner leads and microstrip lines on polyimide film. There is less mutual inductance between lines on the film carrier than with the wiring structure we conventionally use which comprises bonding wire and Al/sub 2/O/sub 3/ circuit board. This structure can reduce the electrical crosstalk between channels on the LD array. A 4-channel LD array sub-module is fabricated employing the above technique, and demonstrated. The module has good frequency characteristics over a bandwidth of 2.3 GHz. The electrical crosstalk between adjacent LDs is less than -30 dB at 1 GHz. This value is about 10 dB lower than with the conventional wiring structure.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129745247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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