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2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)最新文献

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A SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash ADC without time interleaving 无时间交错的SiGe双极6位20gs /s奈奎斯特速率闪存ADC
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798145
Philipp Ritter, Stephane Le Tual, B. Allard, M. Moller
{"title":"A SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash ADC without time interleaving","authors":"Philipp Ritter, Stephane Le Tual, B. Allard, M. Moller","doi":"10.1109/BCTM.2013.6798145","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798145","url":null,"abstract":"An energy efficient plain SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash analog-to-digital converter (ADC) without time interleaving and without track-and-hold is presented. A novel comparator placing concept along with a differential reference ladder is used to take advantage of differential signaling with a pseudo differential comparator architecture. A passive input signal distribution tree is employed to lower the power consumption and its limitations are discussed. The high speed capability of the comparator is studied and its bandwidth requirement is related to its linearity range. The ADC has a total power dissipation of 1 W and exhibits a dynamic linearity of 3.7 ENOB at 20 GS/s and 10 GHz signal frequency, without any calibration or correction. The conversion efficiency is FOM=3.9 pJ/cs.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126783930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Comparative study of HBT ageing in a complementary SiGe:C BiCMOS technology 互补SiGe:C BiCMOS技术中HBT老化的比较研究
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798167
G. Fischer, J. Molina, B. Tillack
{"title":"Comparative study of HBT ageing in a complementary SiGe:C BiCMOS technology","authors":"G. Fischer, J. Molina, B. Tillack","doi":"10.1109/BCTM.2013.6798167","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798167","url":null,"abstract":"Both npn- and pnp-SiGe HBT types of a complementary BiCMOS technology were consistently studied under mixed-mode and reverse stress conditions to check for any ageing mismatches. These were found to be more pronounced under forward than under reverse stress. Long-term stress-tests revealed a not yet described base current degradation “catching-up” under low current stress conditions. The resulting ageing parameters were put together into an ageing function for incorporation into HBT compact models.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 92 mW, 20 dB gain, broadband lumped SiGe amplifier with bandwidth exceeding 67 GHz 一个92 mW, 20 dB增益，带宽超过67 GHz的宽带集总SiGe放大器
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798155
Z. Xuan, R. Ding, T. Baehr‐Jones, M. Hochberg
{"title":"A 92 mW, 20 dB gain, broadband lumped SiGe amplifier with bandwidth exceeding 67 GHz","authors":"Z. Xuan, R. Ding, T. Baehr‐Jones, M. Hochberg","doi":"10.1109/BCTM.2013.6798155","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798155","url":null,"abstract":"A compact, power-efficient broadband amplifier is demonstrated in a 0.13-micron SiGe BiCMOS process. The amplifier uses a lumped design topology with a shunt-feedback Darlington input stage and an emitter-follower buffered cascode post-amplifier stage. The overall amplifier consumes 92 mW DC power, and exhibits 20-dB gain. The reported 67-GHz bandwidth is limited by available test equipment, and the post-extraction simulated 3-dB bandwidth is 82 GHz, which implies a gain-bandwidth (GBW) of 820 GHz. The amplifier features a low group delay variation to enable high data rate. The post-extraction simulated group delay is 13+/-2 ps from 1 GHz to 100 GHz. The chip occupies an area of 0.28 mm2 including pads, and the core area is only 0.04 mm2, which includes all active devices and peaking inductors. This amplifier shows a figure-of-merit GBW/Pdc of 7.3 and 8.9 GHz/mW, assuming bandwidth of 67 GHz and 82 GHz respectively, which are among the best results to date.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129718410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Towards the industrial deployment of the Silicon Photonics technology 迈向硅光子学技术的工业应用
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798162
G. Chiaretti
{"title":"Towards the industrial deployment of the Silicon Photonics technology","authors":"G. Chiaretti","doi":"10.1109/BCTM.2013.6798162","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798162","url":null,"abstract":"Silicon Photonics will become a mature technology at industrial level in one or two years. An overview including the status of the art of this technology is reported, and the main technological issues still to be focused on are discussed. Finally, ST view of the manufacturability status and of volume applications is provided as well as our vision of a Silicon Photonic roadmap.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123396044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4.8–6.8GHz phase-locked loop with power optimized design methodology for dividers 基于功率优化设计方法的4.8-6.8GHz分频锁相环
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798172
Feng Zhao, Jianjun Yu, Joseph Cali, F. Dai, J. Irwin, Andre Aklian
{"title":"A 4.8–6.8GHz phase-locked loop with power optimized design methodology for dividers","authors":"Feng Zhao, Jianjun Yu, Joseph Cali, F. Dai, J. Irwin, Andre Aklian","doi":"10.1109/BCTM.2013.6798172","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798172","url":null,"abstract":"A 4.8-6.8GHz phase-locked loop (PLL) with a power optimized multi-modulus divider (MMD) for wireless and radar applications is presented in this paper. Based on the timing delay analysis and the self-oscillation frequency of the divider cells, the power consumption of the divide-by-two circuit (DTC) and divide-by-2/3 cells can be optimized, and thus minimum power consumption for divider chain can be achieved. To extend the frequency tuning range of the voltage controlled oscillator (VCO) without significant phase noise degradation, PMOS switches are used to reverse bias the parasitic diode. The proposed PLL achieves a measured tuning range of 34% and measured phase noise of -86dBc/Hz@10kHz offset and -114dBc/Hz@1MHz offset with a center frequency of 6.56GHz, and it consumes 64mW from a 2.0V supply voltage. The PLL system for a radar transceiver is implemented in a 0.13μm SiGe technology with a core area of 1.35×0.65mm2.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127711340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Geometry scalable model parameter extraction for mm-wave SiGe-heterojunction transistors 毫米波sige异质结晶体管几何可伸缩模型参数提取
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798160
A. Pawlak, M. Schroter, A. Fox
{"title":"Geometry scalable model parameter extraction for mm-wave SiGe-heterojunction transistors","authors":"A. Pawlak, M. Schroter, A. Fox","doi":"10.1109/BCTM.2013.6798160","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798160","url":null,"abstract":"The observation of negative perimeter collector current in advanced SiGe HBT technologies is explained and a general geometry scaling approach is proposed. Application to mm-wave SiGe-HBTs shows excellent results of HICUM/L2 v2.31 for a wide range of emitter dimensions. Non-monotonic variation of peak fT with emitter dimensions demonstrates the relevance of a geometry scalable compact model for circuit optimization.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132071815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 220–245 GHz switched beam Butler Matrix in 0.13 µm SiGe BiCMOS technology 基于0.13µm SiGe BiCMOS技术的220-245 GHz开关波束巴特勒矩阵
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798158
M. Elkhouly, Ma Yanfei, C. Meliani, F. Ellinger, J. Scheytt
{"title":"A 220–245 GHz switched beam Butler Matrix in 0.13 µm SiGe BiCMOS technology","authors":"M. Elkhouly, Ma Yanfei, C. Meliani, F. Ellinger, J. Scheytt","doi":"10.1109/BCTM.2013.6798158","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798158","url":null,"abstract":"This paper presents a 220-245 GHz 4 way Butler Matrix chip in 0.13μm SiGe BiCMOS technology. The chip features four 230 GHz amplifiers with almost 9 dB of gain. A SP4T switch is integrated to select between the four outputs of the beamforming network. Finally, an amplifier used to compensate the losses of the SP4T is integrated. The chip exhibits 0 dB of insertion gain and draws 104 mA from 3.3 V supply mainly consumed by the amplifiers. The entire chip occupies 1.5 × 2.4 mm2.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130061810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A versatile low-cost smart power technology platform for applications over broad current and voltage ranges 一个多功能的低成本智能电源技术平台，适用于广泛的电流和电压范围
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798152
Zhi Lin, Hao Hu, Junji Cheng, Xingbi Chen
{"title":"A versatile low-cost smart power technology platform for applications over broad current and voltage ranges","authors":"Zhi Lin, Hao Hu, Junji Cheng, Xingbi Chen","doi":"10.1109/BCTM.2013.6798152","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798152","url":null,"abstract":"A versatile low-cost manufacturing technology, which is based on the optimum variation lateral doping technique, is proposed for smart power ICs in this paper. The proposed technology is capable to combine the lateral and vertical high voltage (> 800V) devices on a single chip, which is suitable for applications over broad current ranges. It is fully compatible with BiCMOS process and has been implemented on a standard CMOS line with only 11 masks. Devices with various breakdown voltages, as well as a switched-mode power supply chip, are successfully fabricated on this platform. The measured results are displayed and discussed in detail.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116496467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 57 GHz programmable frequency divider for fractional-N frequency synthesizers 用于分数n频率合成器的57 GHz可编程分频器
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798141
G. Hasenaecker, M. van Delden, N. Pohl, K. Aufinger, T. Musch
{"title":"A 57 GHz programmable frequency divider for fractional-N frequency synthesizers","authors":"G. Hasenaecker, M. van Delden, N. Pohl, K. Aufinger, T. Musch","doi":"10.1109/BCTM.2013.6798141","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798141","url":null,"abstract":"A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. The measured input frequency range is from DC to 57 GHz for division factors in the entire integer range between 12 and 259 as well as 8 and 9. The frequency divider is based on a dual-modulus concept and has been realized in a SiGe bipolar technology (fT/fmax=170/250 GHz). The exceedingly high maximum input frequency has been reached by using emitter-coupled differential circuit technique with a consequent merging of logic operations and D flip-flops. The divider is designed for low power consumption of less than 300mW at a supply voltage of 3.3V. For the intended use in a fractional-N frequency synthesizer for the millimeter wave range, the division ratio is programmable via an 8 bit parallel interface to enable fast modulation of the division factor.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132682155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
GaN RF device technology and applications, present and future GaN射频器件技术和应用，现在和未来
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Pub Date : 2013-09-01 DOI: 10.1109/BCTM.2013.6798154
B. Green, K. Moore, D. Hill, M. CdeBaca, J. Schultz
{"title":"GaN RF device technology and applications, present and future","authors":"B. Green, K. Moore, D. Hill, M. CdeBaca, J. Schultz","doi":"10.1109/BCTM.2013.6798154","DOIUrl":"https://doi.org/10.1109/BCTM.2013.6798154","url":null,"abstract":"Over the last decade, Gallium Nitride (GaN) has emerged as a mainstream RF technology with disruptive performance potential. Here, we present GaN technology in the context of current commercial RF communications applications as well as future applications. We show state of the art >200W, >75% efficient packaged device performance at 2.14 GHz using a 0.6 μm 48 V technology and apply the device technology to a 400 W ultra-small footprint Doherty power amplifier. We also describe extending the 0.6 μm technology to a 0.2 μm gate length that allows for higher fT that will enable future technology for high-efficiency switch-mode amplifiers.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133915652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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