{"title":"A 92 mW, 20 dB gain, broadband lumped SiGe amplifier with bandwidth exceeding 67 GHz","authors":"Z. Xuan, R. Ding, T. Baehr‐Jones, M. Hochberg","doi":"10.1109/BCTM.2013.6798155","DOIUrl":null,"url":null,"abstract":"A compact, power-efficient broadband amplifier is demonstrated in a 0.13-micron SiGe BiCMOS process. The amplifier uses a lumped design topology with a shunt-feedback Darlington input stage and an emitter-follower buffered cascode post-amplifier stage. The overall amplifier consumes 92 mW DC power, and exhibits 20-dB gain. The reported 67-GHz bandwidth is limited by available test equipment, and the post-extraction simulated 3-dB bandwidth is 82 GHz, which implies a gain-bandwidth (GBW) of 820 GHz. The amplifier features a low group delay variation to enable high data rate. The post-extraction simulated group delay is 13+/-2 ps from 1 GHz to 100 GHz. The chip occupies an area of 0.28 mm2 including pads, and the core area is only 0.04 mm2, which includes all active devices and peaking inductors. This amplifier shows a figure-of-merit GBW/Pdc of 7.3 and 8.9 GHz/mW, assuming bandwidth of 67 GHz and 82 GHz respectively, which are among the best results to date.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A compact, power-efficient broadband amplifier is demonstrated in a 0.13-micron SiGe BiCMOS process. The amplifier uses a lumped design topology with a shunt-feedback Darlington input stage and an emitter-follower buffered cascode post-amplifier stage. The overall amplifier consumes 92 mW DC power, and exhibits 20-dB gain. The reported 67-GHz bandwidth is limited by available test equipment, and the post-extraction simulated 3-dB bandwidth is 82 GHz, which implies a gain-bandwidth (GBW) of 820 GHz. The amplifier features a low group delay variation to enable high data rate. The post-extraction simulated group delay is 13+/-2 ps from 1 GHz to 100 GHz. The chip occupies an area of 0.28 mm2 including pads, and the core area is only 0.04 mm2, which includes all active devices and peaking inductors. This amplifier shows a figure-of-merit GBW/Pdc of 7.3 and 8.9 GHz/mW, assuming bandwidth of 67 GHz and 82 GHz respectively, which are among the best results to date.