Philipp Ritter, Stephane Le Tual, B. Allard, M. Moller
{"title":"A SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash ADC without time interleaving","authors":"Philipp Ritter, Stephane Le Tual, B. Allard, M. Moller","doi":"10.1109/BCTM.2013.6798145","DOIUrl":null,"url":null,"abstract":"An energy efficient plain SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash analog-to-digital converter (ADC) without time interleaving and without track-and-hold is presented. A novel comparator placing concept along with a differential reference ladder is used to take advantage of differential signaling with a pseudo differential comparator architecture. A passive input signal distribution tree is employed to lower the power consumption and its limitations are discussed. The high speed capability of the comparator is studied and its bandwidth requirement is related to its linearity range. The ADC has a total power dissipation of 1 W and exhibits a dynamic linearity of 3.7 ENOB at 20 GS/s and 10 GHz signal frequency, without any calibration or correction. The conversion efficiency is FOM=3.9 pJ/cs.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
An energy efficient plain SiGe bipolar 6 bit 20 GS/s Nyquist-rate flash analog-to-digital converter (ADC) without time interleaving and without track-and-hold is presented. A novel comparator placing concept along with a differential reference ladder is used to take advantage of differential signaling with a pseudo differential comparator architecture. A passive input signal distribution tree is employed to lower the power consumption and its limitations are discussed. The high speed capability of the comparator is studied and its bandwidth requirement is related to its linearity range. The ADC has a total power dissipation of 1 W and exhibits a dynamic linearity of 3.7 ENOB at 20 GS/s and 10 GHz signal frequency, without any calibration or correction. The conversion efficiency is FOM=3.9 pJ/cs.