G. Hasenaecker, M. van Delden, N. Pohl, K. Aufinger, T. Musch
{"title":"用于分数n频率合成器的57 GHz可编程分频器","authors":"G. Hasenaecker, M. van Delden, N. Pohl, K. Aufinger, T. Musch","doi":"10.1109/BCTM.2013.6798141","DOIUrl":null,"url":null,"abstract":"A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. The measured input frequency range is from DC to 57 GHz for division factors in the entire integer range between 12 and 259 as well as 8 and 9. The frequency divider is based on a dual-modulus concept and has been realized in a SiGe bipolar technology (fT/fmax=170/250 GHz). The exceedingly high maximum input frequency has been reached by using emitter-coupled differential circuit technique with a consequent merging of logic operations and D flip-flops. The divider is designed for low power consumption of less than 300mW at a supply voltage of 3.3V. For the intended use in a fractional-N frequency synthesizer for the millimeter wave range, the division ratio is programmable via an 8 bit parallel interface to enable fast modulation of the division factor.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 57 GHz programmable frequency divider for fractional-N frequency synthesizers\",\"authors\":\"G. Hasenaecker, M. van Delden, N. Pohl, K. Aufinger, T. Musch\",\"doi\":\"10.1109/BCTM.2013.6798141\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. The measured input frequency range is from DC to 57 GHz for division factors in the entire integer range between 12 and 259 as well as 8 and 9. The frequency divider is based on a dual-modulus concept and has been realized in a SiGe bipolar technology (fT/fmax=170/250 GHz). The exceedingly high maximum input frequency has been reached by using emitter-coupled differential circuit technique with a consequent merging of logic operations and D flip-flops. The divider is designed for low power consumption of less than 300mW at a supply voltage of 3.3V. For the intended use in a fractional-N frequency synthesizer for the millimeter wave range, the division ratio is programmable via an 8 bit parallel interface to enable fast modulation of the division factor.\",\"PeriodicalId\":272941,\"journal\":{\"name\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCTM.2013.6798141\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 57 GHz programmable frequency divider for fractional-N frequency synthesizers
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. The measured input frequency range is from DC to 57 GHz for division factors in the entire integer range between 12 and 259 as well as 8 and 9. The frequency divider is based on a dual-modulus concept and has been realized in a SiGe bipolar technology (fT/fmax=170/250 GHz). The exceedingly high maximum input frequency has been reached by using emitter-coupled differential circuit technique with a consequent merging of logic operations and D flip-flops. The divider is designed for low power consumption of less than 300mW at a supply voltage of 3.3V. For the intended use in a fractional-N frequency synthesizer for the millimeter wave range, the division ratio is programmable via an 8 bit parallel interface to enable fast modulation of the division factor.