T. Laska, M. Munzer, F. Pfirsch, C. Schaeffer, T. Schmidt
{"title":"The Field Stop IGBT (FS IGBT). A new power device concept with a great improvement potential","authors":"T. Laska, M. Munzer, F. Pfirsch, C. Schaeffer, T. Schmidt","doi":"10.1109/ISPSD.2000.856842","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856842","url":null,"abstract":"By a vertical shrink of the NPT IGBT to a structure with a thin n/sup -/ base and a low doped field stop layer a new IGBT can be realized with drastically reduced overall losses. Especially the combination of the field stop concept with a trench transistor cell results in the almost ideal carrier concentration for a device with minimum on state voltage and lowest switching losses.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125726636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MDmesh/sup TM/: innovative technology for high voltage Power MOSFETs","authors":"M. Saggio, D. Fagone, S. Musumeci","doi":"10.1109/ISPSD.2000.856774","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856774","url":null,"abstract":"A new PowerMOSFET device, called MDmesh/sup TM/ (Multiple Drain mesh), that joins the best performance in the Power management market either in static and dynamic behavior is presented. A strong reduction in the silicon conduction losses per area allowed a valuable resize of the device area and a reduction of the used package volume. Moreover, a valuable reduction in device internal capacitance and gate charge has been observed and an optimized switching behavior has been obtained. A deep look inside the device performances will be presented and the main device features will be compared with the ones of a device having the same conduction losses fabricated with a standard technology.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134522267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Hazdra, J. Vobecký, N. Galster, O. Humbel, T. Dalibor
{"title":"A new degree of freedom in diode optimization: arbitrary axial lifetime profiles by means of ion irradiation","authors":"P. Hazdra, J. Vobecký, N. Galster, O. Humbel, T. Dalibor","doi":"10.1109/ISPSD.2000.856787","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856787","url":null,"abstract":"A novel approach to lifetime control in fast recovery power diodes, arbitrary axial lifetime profiles by single-step ion irradiation, is presented. The principle is based on irradiation through a single mask which is inserted between the ion source and the device. The density and lateral/axial structures of the mask determine the final lifetime profile. Experimental results show that this new technique is fully capable to replace multiple single-energy ion irradiations and to guarantee superior diode performance.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"509 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. van der Pol, A. Ludikhuize, H.G.A. Huizing, B. van Velzen, R. Hueting, J.F. Mom, G. van Lijnschoten, G. Hessels, E.F. Hooghoudt, R. van Huizen, M. Swanenberg, J. Egbers, F. van den Elshout, J. Koning, H. Schligtenhorst, J. Soeteman
{"title":"A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications","authors":"J. van der Pol, A. Ludikhuize, H.G.A. Huizing, B. van Velzen, R. Hueting, J.F. Mom, G. van Lijnschoten, G. Hessels, E.F. Hooghoudt, R. van Huizen, M. Swanenberg, J. Egbers, F. van den Elshout, J. Koning, H. Schligtenhorst, J. Soeteman","doi":"10.1109/ISPSD.2000.856836","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856836","url":null,"abstract":"A-BCD is a family of 100 V BCD processes on SOI offering latchup free operation, improved robustness, superior EMC performance, higher packing density, lower mask count, high temperature and higher frequency operation and easier design over bulk silicon technology. A wide range of a passive and active (5/12/25/60 and 100 V) devices are available. Device design tradeoffs for n- and p-type LDMOS and extended drain PMOS are discussed in detail. This and the low mask count makes it a versatile process for cost-sensitive consumer and automotive markets.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123646644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ludikhuize, A. Heringa, R. van Roijen, J. van Zwol
{"title":"Improved device ruggedness by floating buffer ring","authors":"A. Ludikhuize, A. Heringa, R. van Roijen, J. van Zwol","doi":"10.1109/ISPSD.2000.856794","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856794","url":null,"abstract":"An integrated low-substrate-leakage diode structure is considered, operated in reverse breakdown mode, having a parasitic npn transistor. At high current, the Kirk effect, causing shift of the potential by the space charge of moving carriers, leads to high electric fields and causes device degradation. The application of a protective n+ buffer ring around the cathode redistributes field and current and improves the ruggedness. This principle is also successfully applied for improved ESD performance of a lateral DMOST in a Silicon-on-Insulator process.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123652591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal analysis of high power IGBT modules","authors":"Z. Khatir, S. Lefebvre","doi":"10.1109/ISPSD.2000.856823","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856823","url":null,"abstract":"The technology of high power IGBT modules has been improved significantly these last years against thermal fatigue and the first weaknesses related to the bonding die attach have been well enough corrected. Nowadays, the most frequently observed failure mode is the solder layer cracks between copper base plate material and the ceramic. Experimental tests must be completed by numerical simulation tools in order to analyze this type of failure related to power cycling constraints. Thermal simulations of high power IGBT modules based on the boundary element method are described in this paper. A validation of the numerical tool is shown in steady-state and dynamic operations during a power cycle by comparison with experimental measurements. Finally, using the software, a model of solder layer cracks between copper base plate and the DCB ceramic is applied in order to investigate its effect on the thermal constraints.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"397 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experimental study on plasma engineering in 6500 V IGBTs","authors":"T. Wikstrom, F. Bauer, S. Linder, W. Fichtner","doi":"10.1109/ISPSD.2000.856768","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856768","url":null,"abstract":"This paper discusses the design of high-voltage Insulated Gate Bipolar Transistors (IGBTs), especially the effects on the on-state excess carrier distribution and its consequences for the IGBT's on-state, turn-off and Safe Operating Area (SOA) properties. It is concluded that by careful design, considerable robustness is achievable together with total losses that are comparable to a state-of-the-art GCT Thyristor of similar voltage class.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129187636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Ninomiya, J. Takahashi, K. Sugiyama, T. Inoue, S. Hasegawa, T. Ogura, H. Ohashi
{"title":"4500 V trench IEGTs having superior turn-on switching characteristics","authors":"H. Ninomiya, J. Takahashi, K. Sugiyama, T. Inoue, S. Hasegawa, T. Ogura, H. Ohashi","doi":"10.1109/ISPSD.2000.856811","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856811","url":null,"abstract":"Turn-on characteristics of 4500 V trench IEGTs are discussed. First, turn-on switching power loss was measured using an inductive load circuit. As a result, the turn-on switching power loss of trench IEGTs was smaller than that of planer IEGTs because of high density of MOS-channels. Then di/dt ruggedness of trench IEGTs was measured using a LC resonance circuit. It is concluded that trench IEGTs have a sufficiently di/dt ruggedness.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N. Kanekawa, A. Watanabe, Y. Takeuchi, N. Akiyama
{"title":"2.3 kVac 100 MHz multi-channel monolithic isolator IC","authors":"Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N. Kanekawa, A. Watanabe, Y. Takeuchi, N. Akiyama","doi":"10.1109/ISPSD.2000.856832","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856832","url":null,"abstract":"We have developed a multi-channel monolithic isolator IC that can provide 2.3 kVac isolation and 100 MHz signal transmission. This IC uses high voltage on-chip isolator technology using trench isolation with buried oxide on the SOI substrate and 0.4 /spl mu/m CMOS driver and receiver circuits. This technology enables to produce a 4-channel monolithic isolator with an area of 1.5 mm/sup 2/ and a consumption current of 0.5 mA per channel at a frequency of 50 MHz. We have also developed a one-chip modem interface IC that includes the multi-channel isolator and an analog front-end circuit.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127910465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Momota, M. Otsuki, K. Ishii, H. Takubo, Y. Seki
{"title":"Analysis on the low current turn-on behavior of IGBT module","authors":"S. Momota, M. Otsuki, K. Ishii, H. Takubo, Y. Seki","doi":"10.1109/ISPSD.2000.856843","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856843","url":null,"abstract":"This paper presents the noise emission mechanism from IGBT module, which is strongly required to be improved because of EMC regulations. The various 600 V/100 A IGBT module structures were experimentally and numerically tested to improve the current ringing during low current turn-on. As a result, it has been found that the parasitic inductance in the module should be as small as possible to suppress RLC resonant, which consists of parasitic components in the module and the capacitance in the power devices. It is also confirmed that the extra capacitance attached between gate-emitter of IGBT effectively improves the noise emission without increase the switching loss.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127564313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}