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12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)最新文献

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A new generation of power unipolar devices: the concept of the FLoating islands MOS transistor (FLIMOST) 新一代功率单极器件:浮岛MOS晶体管(FLIMOST)的概念
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856775
N. Cezac, F. Morancho, P. Rossel, H. Tranduc, A. Payre-Lavigne
{"title":"A new generation of power unipolar devices: the concept of the FLoating islands MOS transistor (FLIMOST)","authors":"N. Cezac, F. Morancho, P. Rossel, H. Tranduc, A. Payre-Lavigne","doi":"10.1109/ISPSD.2000.856775","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856775","url":null,"abstract":"In this paper, a new vertical DMOS Transistor is proposed, in which floating islands are placed in the drift region. This new structure, called \"FLIMOST\", exhibits improved on-state performance when compared to the conventional VDMOST. For instance, for a breakdown voltage of 900 Volts, the performance is strongly improved in term of specific on-resistance (reduction of about 70% relative to the conventional structure and 40% relative to the silicon limit). Moreover the specific on-resistance theoretical limits of FLIMOST family are determined and compared to those of the \"Superjunction\" MOS Transistor family: this comparison shows the strong interest of the FLIMOSFET in the 200 V-1000 V breakdown voltage range.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122896885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
SiC power devices with low on-resistance for fast switching applications 具有低导通电阻的SiC功率器件，用于快速开关应用
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856809
P. Friedrichs, H. Mitlehner, K. Dohnke, D. Peters, R. Schorner, U. Weinert, E. Baudelot, D. Stephani
{"title":"SiC power devices with low on-resistance for fast switching applications","authors":"P. Friedrichs, H. Mitlehner, K. Dohnke, D. Peters, R. Schorner, U. Weinert, E. Baudelot, D. Stephani","doi":"10.1109/ISPSD.2000.856809","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856809","url":null,"abstract":"Silicon carbide switching devices exhibit superior properties compared to silicon devices. Low specific on-resistance for high breakdown voltages is believed to be the most outstanding feature of SiC power switching devices. In this paper, MOSFETs and JFETs capable to block 1800 V with a specific on-resistance of 47 m/spl Omega/ cm/sup 2/ and 14.5 m/spl Omega/ cm/sup 2/, resp., are discussed. However, there are additional advantages making SiC devices attractive for the system designer. The authors present fast recovery of the 6H-SiC MOSFET reverse diode (Q/sub rr/ 30 nC, t/sub rr/ 20 ns) and fast switching as well as short circuit capability (1 ms) of vertical VJFETs. Finally, a short outlook to future SiC switching devices is given.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122183231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
A new power MOSFET having excellent avalanche capability 一种具有优异雪崩性能的新型功率MOSFET
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856841
T. Uesugi, T. Suzuki, T. Murata, S. Kawaji, H. Tadano
{"title":"A new power MOSFET having excellent avalanche capability","authors":"T. Uesugi, T. Suzuki, T. Murata, S. Kawaji, H. Tadano","doi":"10.1109/ISPSD.2000.856841","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856841","url":null,"abstract":"In this paper, we explore a new concept for improvement of an avalanche capability of a power MOSFET. The concept is to make parasitic bipolar transistors in all over the chip turn on, and to suppress breakdown current crowding. The avalanche capability of an UMOSFET applied this new concept was 1500 mJ. This value was about one order higher than that of a conventional UMOSFET.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123639792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of stripe and cellular geometry for short circuit rated trench IGBT 短路额定沟槽IGBT的条纹和细胞几何比较
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856824
C. Yun, Hyun Chul Kim, Kyu-Hyun Lee, Joo Il Kim, Tae Hoon Kim
{"title":"Comparison of stripe and cellular geometry for short circuit rated trench IGBT","authors":"C. Yun, Hyun Chul Kim, Kyu-Hyun Lee, Joo Il Kim, Tae Hoon Kim","doi":"10.1109/ISPSD.2000.856824","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856824","url":null,"abstract":"600 V trench IGBTs with various cell structures including cellular and stripe geometry are implemented and their device characteristics are compared in terms of short-circuit ruggedness and device performances. The cellular IGBT which employs n+ source EBR and channel generated EBR shows 18 /spl mu/s of SCWT and 1.7 V of Vce,sat while the stripe IGBT shows 16 /spl mu/s and 1.8 V, respectively. Experimental results show that cellular geometry trench IGBT exhibits better short-circuit immunity than the stripe geometry.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124308882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability characterization of LDMOS transistors submitted to multiple energy discharges 多重能量放电条件下LDMOS晶体管的可靠性研究
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856797
J. Bosc, I. Percheron-Garcon, E. Huynh, P. Lance, I. Pagès, J. Dorkel, G. Sarrabayrouse
{"title":"Reliability characterization of LDMOS transistors submitted to multiple energy discharges","authors":"J. Bosc, I. Percheron-Garcon, E. Huynh, P. Lance, I. Pagès, J. Dorkel, G. Sarrabayrouse","doi":"10.1109/ISPSD.2000.856797","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856797","url":null,"abstract":"In this paper, we show on an example how thermal characterization on test vehicles supported by simulation can be used to define a consistent Accelerated Stress Test for power IC's. We describe the reliability program to access the long-term behavior of LDMOS transistors. After the study of the advantages and limitations of the back body diode thermal measurement method, we have investigated in this work the thermal limits of the tested transistors. Then, using a dedicated test bench, we have evaluated the reliability of the devices submitted to repetitive energy discharges and we have studied the observed failure mechanism. Finally, based on these test results, we have set up a reliability database, which helps us to relate the lifetime of the devices and their working temperature. Thanks to this database, LDMOS design and size will be optimized regarding reliability performances.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127880171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 0.8 /spl mu/m-standard CMOS merges one-wire protocol interpreter and 2.5 A-18 V power switch to accomplish low-cost automotive network 一个0.8 /spl mu/m标准的CMOS融合了单线协议解释器和2.5 A- 18v电源开关，实现了低成本的汽车网络
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856804
C. dos Reis Filho, J. Seminario, M. Jara, S. Finco, W. Luque
{"title":"A 0.8 /spl mu/m-standard CMOS merges one-wire protocol interpreter and 2.5 A-18 V power switch to accomplish low-cost automotive network","authors":"C. dos Reis Filho, J. Seminario, M. Jara, S. Finco, W. Luque","doi":"10.1109/ISPSD.2000.856804","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856804","url":null,"abstract":"The paper describes an integrated microsystem, which makes up the node of a one-wire ring-topology network. The developed IC was fabricated in 0.8 /spl mu/m-standard CMOS technology, occupying an area of 12.7 mm/sup 2/. It consists of two sections: A digital section that implements a state machine, which interprets a proprietary data communication protocol and a power section capable of driving loads up to 2.5 A at 18 V.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131480103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Static and dynamic characteristics of 600-V, 10-A trench bipolar junction diodes 600 v, 10-A沟槽双极结二极管的静态和动态特性
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856814
B. You, A.Q. Huang, J. Sin, A. Xu
{"title":"Static and dynamic characteristics of 600-V, 10-A trench bipolar junction diodes","authors":"B. You, A.Q. Huang, J. Sin, A. Xu","doi":"10.1109/ISPSD.2000.856814","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856814","url":null,"abstract":"In this paper, 600-V, 10-A TBJDs were fabricated utilizing a self-aligned trench process, and characterized experimentally. The static and dynamic characteristics of the TBJDs were investigated at both room and elevated temperatures. Compared to the p-i-n diode, the TBJDs were shown to have not only superior reverse recovery characteristics, but also lower on-state voltage drops and the same reverse leakage current levels at elevated temperature.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127849505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS in a 0.35 /spl mu/m CMOS process A 65 V, 0.56 m/spl ω /。在0.35 /spl mu/m的CMOS工艺中
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856838
R. Zhu, V. Parthasarathy, A. Bose, R. Baird, V. Khemka, T. Roggenbauer, D. Collins, S. Chang, P. Hui, M. Ger, M. Zunino
{"title":"A 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS in a 0.35 /spl mu/m CMOS process","authors":"R. Zhu, V. Parthasarathy, A. Bose, R. Baird, V. Khemka, T. Roggenbauer, D. Collins, S. Chang, P. Hui, M. Ger, M. Zunino","doi":"10.1109/ISPSD.2000.856838","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856838","url":null,"abstract":"This paper reports a 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS with a wide safe operating area integrated into a 0.35 /spl mu/m CMOS process. The superior performance of the device is achieved by advanced implantation techniques without additional thermal steps and without resorting to high-tilt implants.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124215945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Experimental measurements of recombination lifetime in proton irradiated power devices 质子辐照功率器件中复合寿命的实验测量
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856826
S. Daliento, A. Sanseverino, P. Spirito, G. Busatto, J. Wiss
{"title":"Experimental measurements of recombination lifetime in proton irradiated power devices","authors":"S. Daliento, A. Sanseverino, P. Spirito, G. Busatto, J. Wiss","doi":"10.1109/ISPSD.2000.856826","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856826","url":null,"abstract":"Experimental measurements of the recombination lifetime profile induced by proton implantation processes are presented. Results show the capability of the differential technique to monitor lifetime engineering processes.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implant spacer optimization for the improvement of power MOSFETs' unclamped inductive switching (UIS) and high temperature breakdown 用于改善功率mosfet非箝位电感开关(UIS)和高温击穿的植入间隔优化
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI: 10.1109/ISPSD.2000.856795
C. Kocon, J. Zeng, R. Stokes
{"title":"Implant spacer optimization for the improvement of power MOSFETs' unclamped inductive switching (UIS) and high temperature breakdown","authors":"C. Kocon, J. Zeng, R. Stokes","doi":"10.1109/ISPSD.2000.856795","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856795","url":null,"abstract":"This paper proposes an improvement to a 30 V N-Channel Power VDMOSFET's UIS and high temperature breakdown voltage capability by using a non-etched 0.0750 /spl mu/m thin oxide spacer as masking for a high dose body implant in lieu of a power industry accepted 0.3 /spl mu/m-0.5 /spl mu/m etched spacer. This thinner non-etched spacer allows for a more highly concentrated and precise body dopant distribution beneath the source region, for a given implant energy, preventing the parasitic BJT from turning on at high current densities. As a consequence the UIS and high temperature (/spl ges/150/spl deg/C) breakdown characteristics are enhanced without increasing threshold voltage or device on-resistance.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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