A 65 V, 0.56 m/spl ω /。在0.35 /spl mu/m的CMOS工艺中

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI:10.1109/ISPSD.2000.856838

R. Zhu, V. Parthasarathy, A. Bose, R. Baird, V. Khemka, T. Roggenbauer, D. Collins, S. Chang, P. Hui, M. Ger, M. Zunino

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引用次数: 5

摘要

本文报道了一种65 V, 0.56 m/spl ω /。具有宽安全操作区域的LDMOS集成到0.35 /spl μ m CMOS工艺中。该设备的优越性能是通过先进的植入技术实现的，无需额外的热步骤，也无需求助于高倾斜植入物。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS in a 0.35 /spl mu/m CMOS process

This paper reports a 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS with a wide safe operating area integrated into a 0.35 /spl mu/m CMOS process. The superior performance of the device is achieved by advanced implantation techniques without additional thermal steps and without resorting to high-tilt implants.

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12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)

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