Implant spacer optimization for the improvement of power MOSFETs' unclamped inductive switching (UIS) and high temperature breakdown

Abstract

This paper proposes an improvement to a 30 V N-Channel Power VDMOSFET's UIS and high temperature breakdown voltage capability by using a non-etched 0.0750 /spl mu/m thin oxide spacer as masking for a high dose body implant in lieu of a power industry accepted 0.3 /spl mu/m-0.5 /spl mu/m etched spacer. This thinner non-etched spacer allows for a more highly concentrated and precise body dopant distribution beneath the source region, for a given implant energy, preventing the parasitic BJT from turning on at high current densities. As a consequence the UIS and high temperature (/spl ges/150/spl deg/C) breakdown characteristics are enhanced without increasing threshold voltage or device on-resistance.