12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)最新文献

{"title":"Single poly EEPROM for smart power IC's","authors":"E. Carman, P. Parris, H. Chaffai, Fabrice Cotdeloup, Serge Debortoii, E. Hemon, J. Lin-Kwang, O. Perat, T. Sicard","doi":"10.1109/ISPSD.2000.856800","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856800","url":null,"abstract":"Smart power integrated circuits need low density memory for applications such as trimming, IC customization, system addresses, and part traceability with few program/erase cycles. Memory solutions must be low cost and demonstrate high reliability in automotive environments. Programmability in the application is an advantage. We have developed a single poly EEPROM that meets these requirements and in addition gives significant die area savings over traditional low cost memory techniques.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114492960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.35 /spl mu/m trench gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching","authors":"A. Narazaki, J. Maruyama, T. Kayumi, H. Hamachi, J. Moritani, S. Hine","doi":"10.1109/ISPSD.2000.856847","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856847","url":null,"abstract":"This paper describes performance of 20 V class N-channel MOSFET using 0.35 /spl mu/m trench gate structure. It has two characteristics mainly. The first is an ultra low on state resistance by shrinking the trench gate width and increasing cell densities. The other is a high destruction immunity during the inductive switching by optimizing a trench depth. The measured specific on-resistance (Ron,sp) is 25% reduction comparing conventional one. Furthermore, this device can provide high avalanche current density during the inductive switching of JD=30 A/mm/sup 2/.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 m/spl Omega//spl middot/mm/sup 2/","authors":"A. Nakagawa, Y. Kawaguchi","doi":"10.1109/ISPSD.2000.856770","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856770","url":null,"abstract":"We propose an improved lateral trench gate MOSFET with a new trench drain contact. The device is predicted to achieve 25 V breakdown voltage and a very low on-resistance of 7.8 m/spl Omega//spl middot/mm/sup 2/, which is by 20% lower than that of previously proposed standard lateral trench gate MOSFETs. The proposed trench contact uniformly distributes the electron current in the drift layer, and effectively reduces the device on-resistance. In the present paper, we also show the detailed electrical characteristics of the fabricated standard trench gate LDMOS. The large current turn-off capability of 1.1/spl times/10/sup 4/ A/cm/sup 2/ was achieved by the fabricated device.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124210801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High temperature static and dynamic characteristics of 3.7 kV high voltage 4H-SiC JBS","authors":"K. Asano, T. Hayashi, R. Saito, Y. Sugawara","doi":"10.1109/ISPSD.2000.856781","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856781","url":null,"abstract":"A new high voltage Junction Barrier controlled Schottky (JBS) diode has been fabricated using 4H-SiC. This diode has some field reduction regions in the active area of a Schottky barrier diode (SBD). These regions can reduce the electric field at the Schottky barrier in the reverse blocking state, and can reduce the leakage current. By adopting the proper SBD metal, fine patterning and optimized structures, we succeeded in improving the trade-off between the blocking voltage (BV) and the specific on-resistance, and achieved a new record high BV of 3.7-3.9 kV and top-level specific on-resistance of 31.4-40.2 m/spl Omega/cm/sup 2/ for the first time. The newly developed JBS has a very fast recovery time t/sub /spl tau//spl tau// of 9.7 ns, which is about 10% that of the Si high-speed diode t/sub /spl tau//spl tau// and high voltage 4H-SiC pn diode. Furthermore, the dynamic characteristics of the developed JBS are almost constant at high temperatures up to 550 K.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"6.5 kV ultra soft & fast recovery diode (U-SFD) with high reverse recovery capability","authors":"M. Mori, H. Kobayashi, Y. Yasuda","doi":"10.1109/ISPSD.2000.856785","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856785","url":null,"abstract":"This paper presents a 65 kV ultra soft and fast recovery diode (U-SFD) for a high power IGBT module. The U-SFD has shallow p type Schottky junctions and deep pn junctions. A high blocking voltage of 6.8 kV even at -40/spl deg/C and a low forward voltage drop (V/sub F/) Of 4.6 V at 125/spl deg/C, which show a positive thermal coefficient, are obtained. The Schottky junctions are effective even for 6.5 kV diodes in achieving better trade-off relationships between V/sub F/ and the reverse recovery loss, V/sub F/ and the reverse recovery peak current, and V/sub F/ and the reverse recovery current change compared to a conventional pn diode. Moreover, the U-SFD with a HiRC (high reverse recovery capability) structure demonstrates good switching durability at a high dc-link voltage of 4.4 kV and at 125/spl deg/C.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124768551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High voltage driver built in a low voltage 0.18 /spl mu/m CMOS for cache redundancy applications in microprocessors","authors":"A. Bergemont, I. Saadat, P. Francis, C. Pichler, H. Haggag, A. Kalnitsky","doi":"10.1109/ISPSD.2000.856789","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856789","url":null,"abstract":"The manufacturability and integration of a high voltage driver transistor built in a 0.18 /spl mu/m CMOS process is demonstrated and evaluated. This paper addresses the driver circuit challenges for fuse programming. Given the low operating voltage nature of the 0.18 /spl mu/m technology, this driver still delivers the required programming energy, yet complying with low voltage limitation of the technology. This transistor is based on extended drain approach and does not require additional masking steps for manufacturing. The transistor is capable of operating up to V/sub d/=15 V and I/sub dsat//W=250 /spl mu/A//spl mu/m at Vg=1.8 V. The reliability of this high voltage driver is also addressed.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124847327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tungsten and tungsten silicide (WSi/sub x/) as gate materials for trench MOSFETs","authors":"S. Ambadi, D. Hanneun, K. Kitt, C. Garcia, J. Pearse","doi":"10.1109/ISPSD.2000.856801","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856801","url":null,"abstract":"High-density and high-speed MOS-integrated devices require low gate resistance. Metallization of the gate electrodes reduces gate sheet resistance, improves switching efficiency, reduces distributed RC propagation delay, and possibly enhances device reliability when delivering power to large inductive loads using large area power MOSFETs. Tungsten (W) and/or tungsten silicide (WSi/sub x/) gates have been developed with this goal for trench power MOSFET applications by chemical vapor deposition (CVD). The deposition techniques employed resulted in good step coverage and provide promising structural integrity against silicon (Si) or W diffusion. The paper discusses the metal/silicided gate development using various approaches.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130427158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices","authors":"M.L. Kniffin, R. Thoma, J. Victory","doi":"10.1109/ISPSD.2000.856799","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856799","url":null,"abstract":"Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127138733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2000 International Symposium On Power Semiconductor Devices And IC's","authors":"","doi":"10.1109/ISPSD.2000.856761","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856761","url":null,"abstract":"ing is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to: IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1 331. '' All rights reserved. Copyright 02000 by the Institute of Electrical and Electronics Engineers, Inc. IEEE Catalog Number 00CH37094 ISBN 0-7803-6269-1 0-7803-6270-5 (Casebound Edition) 0-7803-6271 -3 (Microfiche Edition) Library of Congress 00-001 59 ISPSO’1000, May 22-25, TouIouie, France Chair’s Message On behalf of the ISPSD Conference Committee, I would like to welcome you to the 12th International Symposium on Power Semiconductor Devices and IC’s (ISPSD’2000). ISPSD provides a yearly international forum for technical discussion in all areas of Power Semiconductor Devices, Power ICs and their applications. This conference has grown to become today the most important international conference in this field. Fundamentally international, i t has the very peculiarity to be held each year, not simply in a different place, but in a different “continent” with a rotation throughout the world from Japan, to North America and to Europe. Following last year very successful meeting in Toronto, Canada, the Symposium returns for the third time to Europe, After Davos, Switzerland, in 1994 and Weimar, Germany in 1997, Toulouse, France, will host the Symposium for the very famous year 3000. The plenary invited talks on Monday afternoon mirror the geographical rotation of the conference and feature the following presentations: From Japan: “Progress in Wide-Bandgap Semiconductor S i c for Power Devices”, by Hiroyuki Matsunami from Kyoto University. From Europe: “A Review of RESURF Technology”, by Adriaan W. Ludikhuize, Philips Research, Eindhoven, The Netherlands. From North America: “Beyond Y2K: Technology Convergence as a Driver of Future Low-Voltage Power Management Semiconductors”, by Richard K. Williams, Advanced Analogic Technologies, Inc., Sunnyvale CA. Interestingly, these invited talks also fairly represent the domains covered by ISPSD, i.e. materials, devices and applications. The number of submitted abstracts reached a total number of 1.59. From this number, 65 where from “pure” academic research groups, 68 from “pure” industrial research teams and 26 where co-signed between universities and industries, emphasising their mutual strong collaboration in the power device domain. The global character of ISPSD is reflected by submissions originating from 2.5 countries; 40.8% from Europe, 34.5% from America, 15.9% from Japan, 11.4% from Asia and 7.4% from the rest of the world. 39 papers were accepted for ora1 presentation with anothe","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}