{"title":"MDmesh/sup TM/: innovative technology for high voltage Power MOSFETs","authors":"M. Saggio, D. Fagone, S. Musumeci","doi":"10.1109/ISPSD.2000.856774","DOIUrl":null,"url":null,"abstract":"A new PowerMOSFET device, called MDmesh/sup TM/ (Multiple Drain mesh), that joins the best performance in the Power management market either in static and dynamic behavior is presented. A strong reduction in the silicon conduction losses per area allowed a valuable resize of the device area and a reduction of the used package volume. Moreover, a valuable reduction in device internal capacitance and gate charge has been observed and an optimized switching behavior has been obtained. A deep look inside the device performances will be presented and the main device features will be compared with the ones of a device having the same conduction losses fabricated with a standard technology.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"62","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 62
Abstract
A new PowerMOSFET device, called MDmesh/sup TM/ (Multiple Drain mesh), that joins the best performance in the Power management market either in static and dynamic behavior is presented. A strong reduction in the silicon conduction losses per area allowed a valuable resize of the device area and a reduction of the used package volume. Moreover, a valuable reduction in device internal capacitance and gate charge has been observed and an optimized switching behavior has been obtained. A deep look inside the device performances will be presented and the main device features will be compared with the ones of a device having the same conduction losses fabricated with a standard technology.