A. Ludikhuize, A. Heringa, R. van Roijen, J. van Zwol
{"title":"Improved device ruggedness by floating buffer ring","authors":"A. Ludikhuize, A. Heringa, R. van Roijen, J. van Zwol","doi":"10.1109/ISPSD.2000.856794","DOIUrl":null,"url":null,"abstract":"An integrated low-substrate-leakage diode structure is considered, operated in reverse breakdown mode, having a parasitic npn transistor. At high current, the Kirk effect, causing shift of the potential by the space charge of moving carriers, leads to high electric fields and causes device degradation. The application of a protective n+ buffer ring around the cathode redistributes field and current and improves the ruggedness. This principle is also successfully applied for improved ESD performance of a lateral DMOST in a Silicon-on-Insulator process.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An integrated low-substrate-leakage diode structure is considered, operated in reverse breakdown mode, having a parasitic npn transistor. At high current, the Kirk effect, causing shift of the potential by the space charge of moving carriers, leads to high electric fields and causes device degradation. The application of a protective n+ buffer ring around the cathode redistributes field and current and improves the ruggedness. This principle is also successfully applied for improved ESD performance of a lateral DMOST in a Silicon-on-Insulator process.