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2009 Proceedings of ESSCIRC最新文献

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A highly linear, differential gyrator in 65nm CMOS for reconfigurable GHz applications 高度线性，差分旋转器在65nm CMOS为可重构GHz应用
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326031
O. Schmitz, S. Hampel, K. Mertens, M. Tiebout, I. Rolfes
{"title":"A highly linear, differential gyrator in 65nm CMOS for reconfigurable GHz applications","authors":"O. Schmitz, S. Hampel, K. Mertens, M. Tiebout, I. Rolfes","doi":"10.1109/ESSCIRC.2009.5326031","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326031","url":null,"abstract":"This work presents the design, implementation and measurement results of a novel, gyrator-based active inductor circuit in a 1.2 V 65nm CMOS technology. By solely employing stacked nMOS-pMOS transistor combinations, the proposed differential gyrator achieves a maximal self-resonance frequency of approximately 18 GHz and features high linearity with a current consumption of only 6 mA, therefore representing an attractive candidate for radio-frequency applications. The proposed active inductor is combined with additional circuitry and switchable capacitors in order to form an inductorless, reconfigurable RF amplifier. The comparison of measurement and simulation data in terms of scattering parameters and output referred compression verifies the active inductor's functionality.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123635680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS 基于半积分次谐波锁定的0.18µm CMOS低相位噪声注入锁相差动环压控振荡器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325965
Yuka Kobayashi, S. Amakawa, N. Ishihara, K. Masu
{"title":"A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS","authors":"Yuka Kobayashi, S. Amakawa, N. Ishihara, K. Masu","doi":"10.1109/ESSCIRC.2009.5325965","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325965","url":null,"abstract":"Design and implementation of a CMOS differential ring-VCO that locks at half-integral (1.5, 2.5, 3.5, ⋯) as well as integral (1, 2, 3, ⋯) multiples of the injected reference frequency fref are presented. The advantage of half-integral subharmonic locking is that, for a given VCO output frequency step, the output phase noise can be lowered than when using integral subharmonic locking because of the higher (2x) reference frequency. For example, the 1-MHz-offset phase noise at a VCO output frequency of 1.5GHz was −136 dBc/Hz when locked to an integral subharmonic of fref = 0.5 GHz, whereas it was as low as −139 dBc/Hz when locked to a half-integral subharmonic of fref = 1.0 GHz. The ring-VCO was fabricated with a 0.18µm CMOS process. An explanation is given as to why it locks to half-integral subharmonics and how such an oscillator could be designed. Half-integral or, more generally, nonintegral subharmonic locking could make an effective means to reduce the phase noise of high-resolution injection-locked VCOs.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121894556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A yield centric statistical design method for optimization of the SRAM active column 以产率为中心的SRAM有源柱优化统计设计方法
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325954
T. Doorn, J. Croon, J. T. Maten, A. D. Bucchianico
{"title":"A yield centric statistical design method for optimization of the SRAM active column","authors":"T. Doorn, J. Croon, J. T. Maten, A. D. Bucchianico","doi":"10.1109/ESSCIRC.2009.5325954","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325954","url":null,"abstract":"For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier size.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126286068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A double balanced power amplifier for S-band phased arrays in SiGe BiCMOS SiGe BiCMOS s波段相控阵双平衡功率放大器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325990
H. Erkens, R. Wunderlich, S. Heinen
{"title":"A double balanced power amplifier for S-band phased arrays in SiGe BiCMOS","authors":"H. Erkens, R. Wunderlich, S. Heinen","doi":"10.1109/ESSCIRC.2009.5325990","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325990","url":null,"abstract":"A differential balanced (= ‘double balanced’) power amplifier has been implemented in a 0.25 µm SiGe BiCMOS technology. It delivers most of its maximum output power even with an active load disturbing the PA output with parasitic high power signals. Other features are its excellent output return loss and four point on-chip power generation, decreasing coupling effects. The differential input quadrature splitter and both differential amplifier cores have been integrated on one die measuring 1400 µm x 900 µm. The device has been optimized for operation at S-band (2.9 GHz … 3.1GHz) and reaches a small signal gain of 51 dB with a maximum saturated output power of 24.2 dBm. The double balanced PA withstands active load signals of 18dBm with a low output power penalty of 2.5 dB. Its high tolerance against parasitic element coupling makes the highly integrated device an excellent choice for transmit/receive modules of low-cost commercial phased arrays.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
122 GHz low-noise-amplifier in sige technology 122ghz低噪声放大放大技术
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325945
W. Winkler, W. Debski, B. Heinemann, F. Korndörfer, H. Rücker, K. Schmalz, C. Scheytt, B. Tillack
{"title":"122 GHz low-noise-amplifier in sige technology","authors":"W. Winkler, W. Debski, B. Heinemann, F. Korndörfer, H. Rücker, K. Schmalz, C. Scheytt, B. Tillack","doi":"10.1109/ESSCIRC.2009.5325945","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325945","url":null,"abstract":"The paper presents two types of 122 GHz low-noise-amplifiers (LNA) fabricated in SiGe BiCMOS technology. The amplifier design takes advantage of a novel transmission line structure with thick metal ground-shield on top of the MMIC. The circuit is a two-stage cascode topology utilizing transmission lines for input, output and inter-stage matching. The amplifiers are designed for high gain, minimum noise figure and low power consumption. Measurements show a gain of 13.5 dB and a noise figure of 9.6 dB at 122 GHz. The power consumption is 52mW from a 3.5 Volt supply. The other version of the LNA with transformer coupling to the output instead of capacitive coupling has slightly lower gain. The amplifier is intended for the use in ISM-band radar and communication systems, wide-band communication systems and in radar imaging systems.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 0.5 V feedforward delta-sigma modulator with inverter-based integrator 一个0.5 V前馈δ - σ调制器与基于逆变器的积分器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325936
Jun Wang, T. Matsuoka, K. Taniguchi
{"title":"A 0.5 V feedforward delta-sigma modulator with inverter-based integrator","authors":"Jun Wang, T. Matsuoka, K. Taniguchi","doi":"10.1109/ESSCIRC.2009.5325936","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325936","url":null,"abstract":"This paper presents an inverter-based switched-capacitor integrator for 0.5 V low-voltage applications. The proposed integrator utilizing floating voltage source and forward body bias obtains high performance as well as good independence of variations in process and temperature. It is applied to a 0.5 V feedforward AD modulator. The test results indicate that the designed AD modulator achieves a peak SNDR of 71 dB in a 78 kHz bandwidth, and the core power consumption is only 860 µW. This work is designed in a standard 0.18 µm CMOS process.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129367300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
An 8th-order MASH delta-sigma with an OSR of 3 8阶MASH δ - σ， OSR为3
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325962
T. Caldwell, D. Johns
{"title":"An 8th-order MASH delta-sigma with an OSR of 3","authors":"T. Caldwell, D. Johns","doi":"10.1109/ESSCIRC.2009.5325962","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325962","url":null,"abstract":"This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The future of high frequency circuit design 未来的高频电路设计
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325926
A. Hajimiri
{"title":"The future of high frequency circuit design","authors":"A. Hajimiri","doi":"10.1109/ESSCIRC.2009.5325926","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325926","url":null,"abstract":"The cut-off wavelengths of integrated silicon transistors have exceeded the die sizes of the chips being fabricated with them. Combined with the ability to integrate billions of transistors on the same die, this size-wavelength cross-over has produced a unique opportunity for a completely new class of holistic circuit design combining electromagnetics, device physics, circuits, and communication system theory in one place. In this paper, we discuss some of these opportunities and their associated challenges in greater detail and provide a few of examples of how they can be used in practice.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122144971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A wideband 0 to 60 dB CMOS variable gain amplifier for IR-UWB I/Q receivers 一种用于IR-UWB I/Q接收机的宽带0 ~ 60db CMOS可变增益放大器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325977
D. Barras, H. Jaeckel, W. Hirt
{"title":"A wideband 0 to 60 dB CMOS variable gain amplifier for IR-UWB I/Q receivers","authors":"D. Barras, H. Jaeckel, W. Hirt","doi":"10.1109/ESSCIRC.2009.5325977","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325977","url":null,"abstract":"This paper reports on the realization of a variable gain amplifier (VGA) with an automatic gain control (AGC) loop for impulse-radio ultra-wideband (IR-UWB) signals. The circuit shows a gain range between 0 and 60 dB and a −3 dB bandwidth larger than 180 MHz over the whole gain range. The VGA also features a dual channel implementation for quadrature signal demodulation and shows very small I/Q imbalance. The circuit is fabricated in 0.18 µm technology, draws less than 5mA from a 1.8 V supply voltage and occpies an area 1 mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125142796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 60 µW low-power low-voltage power management unit for a self-powered system based on low-cost piezoelectric powering generators 基于低成本压电发电机的自供电系统的60µW低功耗低压电源管理单元
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326030
J. Colomer-Farrarons, P. Miribel-Català, A. Saiz-Vela, J. Samitier
{"title":"A 60 µW low-power low-voltage power management unit for a self-powered system based on low-cost piezoelectric powering generators","authors":"J. Colomer-Farrarons, P. Miribel-Català, A. Saiz-Vela, J. Samitier","doi":"10.1109/ESSCIRC.2009.5326030","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326030","url":null,"abstract":"This paper presents the architecture of a novel implementation of an integrated self-powered system based on piezoelectric vibrations in a 0.13µm technology. The electromechanical transduction is performed by using a low-cost commercial piezoelectric, working at low frequencies, with voltages up to 2.5V. The system is conceived as a System In a Package (SiP). The full integrated system is adapted to work with low-voltage and low-power conditions. The full custom power management circuit is used to charge a storage capacitor (super capacitor), from which the stored energy will be used to power, by controlled cycles of discharge operation of a very low power wireless sensor node that could be used in heavy machinery monitoring. Each circuitry block of the power management circuitry is presented and discussed. The simulated studies are fully validated by experimental tests. The experimental consumption of the power management unit is 67µW, approach to the theoretical expected value of 60µW.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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