An 8th-order MASH delta-sigma with an OSR of 3

Abstract

This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.