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2009 Proceedings of ESSCIRC最新文献

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Assessment of the impact of technology scaling on the performance of LC-VCOs 技术规模对lc - vco性能影响的评估
2009 Proceedings of ESSCIRC Pub Date : 2009-11-13 DOI: 10.1109/ESSDERC.2009.5331398
D. Ponton, G. Knoblinger, A. Roithmeier, M. Tiebout, M. Fulde, P. Palestri
{"title":"Assessment of the impact of technology scaling on the performance of LC-VCOs","authors":"D. Ponton, G. Knoblinger, A. Roithmeier, M. Tiebout, M. Fulde, P. Palestri","doi":"10.1109/ESSDERC.2009.5331398","DOIUrl":"https://doi.org/10.1109/ESSDERC.2009.5331398","url":null,"abstract":"This paper analyzes the scaling of LC Voltage Controlled Oscillator (LC-VCO) implemented in advanced Planar CMOS technologies. An LC-VCO for GSM applications, has been designed in state-of-the-art 45/40nm and 32nm CMOS technologies, exploiting different Front- and Back-End Of Line (FEOL/BEOL) options. The designs are compared with each other and with recent literature in terms of power and Phase-Noise performance.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128258496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high efficiency and compact size 65nm power management module with 1.2v low-voltage PWM controller for UWB system application 一款高效紧凑的65nm电源管理模块，具有1.2v低压PWM控制器，适用于超宽带系统应用
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326007
Yu-Huei Lee, Shih-Jung Wang, Yao-Yi Yang, Kuo-Lin Zheng, Po-Fung Chen, C. Hsieh, Ming-Hsin Huang, Yu-Nong Tsai, Yu-Zhou Ke, Ke-Horng Chen, Yi-Kuang Chen, Chen-Chih Huang, Ying-Hsi Lin
{"title":"A high efficiency and compact size 65nm power management module with 1.2v low-voltage PWM controller for UWB system application","authors":"Yu-Huei Lee, Shih-Jung Wang, Yao-Yi Yang, Kuo-Lin Zheng, Po-Fung Chen, C. Hsieh, Ming-Hsin Huang, Yu-Nong Tsai, Yu-Zhou Ke, Ke-Horng Chen, Yi-Kuang Chen, Chen-Chih Huang, Ying-Hsi Lin","doi":"10.1109/ESSCIRC.2009.5326007","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326007","url":null,"abstract":"This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm2 silicon die area.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121803683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? 从平面到FinFET的进一步CMOS缩放迁移:SOI或体?
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325993
T. Chiarella, L. Witters, A. Mercha, C. Kerner, R. Dittrich, M. Rakowski, C. Ortolland, L. Ragnarsson, B. Parvais, A. D. Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, T. Hoffmann
{"title":"Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?","authors":"T. Chiarella, L. Witters, A. Mercha, C. Kerner, R. Dittrich, M. Rakowski, C. Ortolland, L. Ragnarsson, B. Parvais, A. D. Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, T. Hoffmann","doi":"10.1109/ESSCIRC.2009.5325993","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325993","url":null,"abstract":"The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL 6 ~ 11ghz多相锁相环的设计与相位噪声分析
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326023
G. V. Büren, D. Barras, H. Jäckel, A. Huber, C. Kromer, M. Kossel
{"title":"Design and phase noise analysis of a multiphase 6 to 11 GHz PLL","authors":"G. V. Büren, D. Barras, H. Jäckel, A. Huber, C. Kromer, M. Kossel","doi":"10.1109/ESSCIRC.2009.5326023","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326023","url":null,"abstract":"This paper presents the design, the phase noise analysis and measurement results of a fourth-order phase-locked loop (PLL) circuit. The PLL is composed of a four-stage inductorless ring oscillator, a 1/16-divider, phase-frequency detector (PFD), charge pump and loop filter, which all are fully differential circuits. A tuning range of 6 to 11 GHz is achieved using delay interpolation elements in the ring oscillator. For jitter minimization, we analyze the noise contribution of each building block, identify the largest noise contributors, and evaluate the total PLL phase noise in s- and z-domain. The measured RMS jitter of 18 mUI agrees well with the predicted value of 15 mUI from our noise analysis. The PLL is fabricated in 90-nm bulk CMOS, consumes a current of 45mA at 1.1V and occupies an area of 0.1 mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Ultra low power detection circuits in 130nm CMOS for a wireless UWB localization system 用于无线超宽带定位系统的130nm CMOS超低功耗检测电路
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325949
C. D. Roover, M. Steyaert
{"title":"Ultra low power detection circuits in 130nm CMOS for a wireless UWB localization system","authors":"C. D. Roover, M. Steyaert","doi":"10.1109/ESSCIRC.2009.5325949","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325949","url":null,"abstract":"This paper presents two detection circuits with an ultra low power consumption in the nW-range. A voltage detection circuit is designed and measured of which the output switches if the supply voltage reaches 1V. It consumes an average current of merely 3nA. Also a power dip detection circuit is designed and measured which detects if an RF-signal is present at the input. The minimal needed input power is −24.5dBm, and it operates from a supply voltage of 0.5V up to 1V and consumes only 5nW to 65nW respectively when active. It operates with a carrier frequency from 40MHz up to 900MHz. It can serve as an OOK-demodulator for bitrates up to 6.67kbps. The die area of both circuits combined, excluding buffers and including decoupling capacitors, is 310µm×550µm.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114300330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 5.8GHz LC-based digitally controlled oscillator with 20kHz frequency resolution and 37 % tuning range 一个5.8GHz基于lc的数字控制振荡器，频率分辨率为20kHz，调谐范围为37%
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326004
Rachid El Waffaoui, Simon Lee
{"title":"A 5.8GHz LC-based digitally controlled oscillator with 20kHz frequency resolution and 37 % tuning range","authors":"Rachid El Waffaoui, Simon Lee","doi":"10.1109/ESSCIRC.2009.5326004","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326004","url":null,"abstract":"This paper reports an LC-based digitally controlled oscillator (DCO) in 65nm CMOS, key component in a digital phase locked loop, with an enhanced frequency resolution and extended tuning range. It has a center frequency of 5.8GHz and a tuning range of 1800MHz. The finest frequency step is about 20kHz. The oscillator exhibits a phase noise of −100dBc/Hz at 100kHz frequency offset from 4.9GHz. The DCO draws 4mA current from 1.8V supply.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range 宽电源、宽频率范围电流型SMPS电容耦合电流传感及自动测距斜率补偿
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326034
S. Herzer, S. Kulkarni, M. Jankowski, J. Neidhardt, B. Wicht
{"title":"Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range","authors":"S. Herzer, S. Kulkarni, M. Jankowski, J. Neidhardt, B. Wicht","doi":"10.1109/ESSCIRC.2009.5326034","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326034","url":null,"abstract":"Techniques for high impedance current sensing and slope compensation, common challenges for current mode switched mode power supplies (SMPS), are presented. DCR sensing, limited by conventional low impedance sensing techniques, is thus possible, enabling power efficiency gains. Auto-ranging slope compensation based on a multiplication of input voltage V<inf>IN</inf> and switching frequency f<inf>sw</inf> allows for truer current mode operation and superior line transient response for a wide range of V<inf>IN</inf> and f<inf>sw</inf>. The techniques are demonstrated in an automotive-class 60V V<inf>IN</inf> buck controller at 150–600kHz in a 0.35µm BiCMOS technology. Offset error ≪3mV over 0–10V and single-cycle stable current loop response are measured.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128717171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Scaling beyond CMOS: Turing-Heisenberg Rapproachment 超越CMOS的扩展:图灵-海森堡方法
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325930
V. Zhirnov, R. Cavin
{"title":"Scaling beyond CMOS: Turing-Heisenberg Rapproachment","authors":"V. Zhirnov, R. Cavin","doi":"10.1109/ESSCIRC.2009.5325930","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325930","url":null,"abstract":"The primary objective of this study is to explore the connection of the device physics in the Boltzmann-Heisenberg limits and the parameters of the digital circuits implemented from these devices. We offer an abstraction of a Minimal Turing Machine built from the limiting devices and circuits, thus Turing-Heisenberg Rapprochement. The analysis suggests a possible limit to computational performance similar to the Carnot efficiency limit for heat engines.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS 一个19GHz, 250pJ/bit的非线性BPSK解调器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325959
J. Macias-Montero, H. Yan, A. Akhnoukh, L. D. Vreede, J. Long, J. López-Villegas, J. Pekarik
{"title":"A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS","authors":"J. Macias-Montero, H. Yan, A. Akhnoukh, L. D. Vreede, J. Long, J. López-Villegas, J. Pekarik","doi":"10.1109/ESSCIRC.2009.5325959","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325959","url":null,"abstract":"A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"37 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120889190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-cost feedback-enabled LNAs in 45nm CMOS 45纳米CMOS低成本反馈lna
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326024
J. Borremans, S. Thijs, M. Dehan, A. Mercha, P. Wambacq
{"title":"Low-cost feedback-enabled LNAs in 45nm CMOS","authors":"J. Borremans, S. Thijs, M. Dehan, A. Mercha, P. Wambacq","doi":"10.1109/ESSCIRC.2009.5326024","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326024","url":null,"abstract":"Multistandard, flexible and wideband front-ends emerge to cover an increasing variety of wireless standards. Meanwhile, expensive downscaled CMOS calls for robust, area-efficient circuit solutions. This work presents such low-area, low-cost feedback-enabled LNAs in 45nm CMOS. Wideband or narrow-band operation, exceeding 10GHz is achieved by selecting an appropriate compact load. Several state-of-the-art versions are presented such as a 0.008mm2 3-10GHz UWB LNA with flat 3dB NF consuming 7mW, and a 0.02 mm2 8-16GHz LNA with 4dB NF, 17dB gain and 4.2kV ESD protection.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126441133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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