一个19GHz, 250pJ/bit的非线性BPSK解调器

2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI:10.1109/ESSCIRC.2009.5325959

J. Macias-Montero, H. Yan, A. Akhnoukh, L. D. Vreede, J. Long, J. López-Villegas, J. Pekarik

{"title":"一个19GHz, 250pJ/bit的非线性BPSK解调器","authors":"J. Macias-Montero, H. Yan, A. Akhnoukh, L. D. Vreede, J. Long, J. López-Villegas, J. Pekarik","doi":"10.1109/ESSCIRC.2009.5325959","DOIUrl":null,"url":null,"abstract":"A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"37 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS\",\"authors\":\"J. Macias-Montero, H. Yan, A. Akhnoukh, L. D. Vreede, J. Long, J. López-Villegas, J. Pekarik\",\"doi\":\"10.1109/ESSCIRC.2009.5325959\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"37 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325959\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

一种低复杂度二进制相移键控(BPSK)解调器实现了无需外部元件的超低功耗工作。采用二次谐波注入锁定和模拟倍增技术恢复19GHz bpsk调制载波的数据。0.35mm2的90nm CMOS测试芯片的误码率(BER)为10Mbps，可与经典的DBPSK检测相媲美。原型解调器在0.8V时仅消耗2.5mW，或250pJ/bit。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS

A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 Proceedings of ESSCIRC

自引率

0.00%

发文量