A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS

Abstract

A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.