Design and phase noise analysis of a multiphase 6 to 11 GHz PLL

Abstract

This paper presents the design, the phase noise analysis and measurement results of a fourth-order phase-locked loop (PLL) circuit. The PLL is composed of a four-stage inductorless ring oscillator, a 1/16-divider, phase-frequency detector (PFD), charge pump and loop filter, which all are fully differential circuits. A tuning range of 6 to 11 GHz is achieved using delay interpolation elements in the ring oscillator. For jitter minimization, we analyze the noise contribution of each building block, identify the largest noise contributors, and evaluate the total PLL phase noise in s- and z-domain. The measured RMS jitter of 18 mUI agrees well with the predicted value of 15 mUI from our noise analysis. The PLL is fabricated in 90-nm bulk CMOS, consumes a current of 45mA at 1.1V and occupies an area of 0.1 mm2.